340 lines
11 KiB
C
340 lines
11 KiB
C
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PSCI_PRIVATE_H
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#define PSCI_PRIVATE_H
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <lib/bakery_lock.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/psci/psci.h>
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#include <lib/spinlock.h>
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/*
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* The PSCI capability which are provided by the generic code but does not
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* depend on the platform or spd capabilities.
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*/
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#define PSCI_GENERIC_CAP \
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(define_psci_cap(PSCI_VERSION) | \
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define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
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define_psci_cap(PSCI_FEATURES))
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/*
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* The PSCI capabilities mask for 64 bit functions.
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*/
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#define PSCI_CAP_64BIT_MASK \
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(define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \
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define_psci_cap(PSCI_CPU_ON_AARCH64) | \
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define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
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define_psci_cap(PSCI_MIG_AARCH64) | \
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define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \
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define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \
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define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \
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define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \
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define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \
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define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \
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define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64))
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/*
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* Helper functions to get/set the fields of PSCI per-cpu data.
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*/
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static inline void psci_set_aff_info_state(aff_info_state_t aff_state)
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{
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set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state);
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}
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static inline aff_info_state_t psci_get_aff_info_state(void)
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{
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return get_cpu_data(psci_svc_cpu_data.aff_info_state);
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}
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static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx)
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{
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return get_cpu_data_by_index(idx,
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psci_svc_cpu_data.aff_info_state);
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}
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static inline void psci_set_aff_info_state_by_idx(unsigned int idx,
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aff_info_state_t aff_state)
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{
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set_cpu_data_by_index(idx,
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psci_svc_cpu_data.aff_info_state, aff_state);
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}
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static inline unsigned int psci_get_suspend_pwrlvl(void)
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{
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return get_cpu_data(psci_svc_cpu_data.target_pwrlvl);
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}
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static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl)
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{
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set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl);
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}
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static inline void psci_set_cpu_local_state(plat_local_state_t state)
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{
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set_cpu_data(psci_svc_cpu_data.local_state, state);
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}
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static inline plat_local_state_t psci_get_cpu_local_state(void)
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{
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return get_cpu_data(psci_svc_cpu_data.local_state);
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}
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static inline plat_local_state_t psci_get_cpu_local_state_by_idx(
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unsigned int idx)
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{
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return get_cpu_data_by_index(idx,
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psci_svc_cpu_data.local_state);
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}
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/* Helper function to identify a CPU standby request in PSCI Suspend call */
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static inline bool is_cpu_standby_req(unsigned int is_power_down_state,
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unsigned int retn_lvl)
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{
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return (is_power_down_state == 0U) && (retn_lvl == 0U);
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}
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/*******************************************************************************
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* The following two data structures implement the power domain tree. The tree
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* is used to track the state of all the nodes i.e. power domain instances
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* described by the platform. The tree consists of nodes that describe CPU power
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* domains i.e. leaf nodes and all other power domains which are parents of a
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* CPU power domain i.e. non-leaf nodes.
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******************************************************************************/
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typedef struct non_cpu_pwr_domain_node {
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/*
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* Index of the first CPU power domain node level 0 which has this node
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* as its parent.
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*/
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unsigned int cpu_start_idx;
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/*
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* Number of CPU power domains which are siblings of the domain indexed
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* by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
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* -> cpu_start_idx + ncpus' have this node as their parent.
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*/
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unsigned int ncpus;
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/*
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* Index of the parent power domain node.
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* TODO: Figure out whether to whether using pointer is more efficient.
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*/
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unsigned int parent_node;
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plat_local_state_t local_state;
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unsigned char level;
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/* For indexing the psci_lock array*/
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unsigned char lock_index;
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} non_cpu_pd_node_t;
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typedef struct cpu_pwr_domain_node {
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u_register_t mpidr;
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/*
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* Index of the parent power domain node.
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* TODO: Figure out whether to whether using pointer is more efficient.
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*/
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unsigned int parent_node;
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/*
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* A CPU power domain does not require state coordination like its
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* parent power domains. Hence this node does not include a bakery
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* lock. A spinlock is required by the CPU_ON handler to prevent a race
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* when multiple CPUs try to turn ON the same target CPU.
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*/
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spinlock_t cpu_lock;
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} cpu_pd_node_t;
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/*******************************************************************************
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* The following are helpers and declarations of locks.
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******************************************************************************/
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#if HW_ASSISTED_COHERENCY
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/*
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* On systems where participant CPUs are cache-coherent, we can use spinlocks
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* instead of bakery locks.
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*/
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#define DEFINE_PSCI_LOCK(_name) spinlock_t _name
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#define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name)
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/* One lock is required per non-CPU power domain node */
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DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
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/*
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* On systems with hardware-assisted coherency, make PSCI cache operations NOP,
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* as PSCI participants are cache-coherent, and there's no need for explicit
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* cache maintenance operations or barriers to coordinate their state.
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*/
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static inline void psci_flush_dcache_range(uintptr_t __unused addr,
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size_t __unused size)
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{
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/* Empty */
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}
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#define psci_flush_cpu_data(member)
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#define psci_inv_cpu_data(member)
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static inline void psci_dsbish(void)
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{
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/* Empty */
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}
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static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
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{
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spin_lock(&psci_locks[non_cpu_pd_node->lock_index]);
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}
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static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
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{
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spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]);
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}
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#else /* if HW_ASSISTED_COHERENCY == 0 */
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/*
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* Use bakery locks for state coordination as not all PSCI participants are
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* cache coherent.
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*/
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#define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name)
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#define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name)
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/* One lock is required per non-CPU power domain node */
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DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
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/*
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* If not all PSCI participants are cache-coherent, perform cache maintenance
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* and issue barriers wherever required to coordinate state.
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*/
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static inline void psci_flush_dcache_range(uintptr_t addr, size_t size)
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{
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flush_dcache_range(addr, size);
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}
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#define psci_flush_cpu_data(member) flush_cpu_data(member)
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#define psci_inv_cpu_data(member) inv_cpu_data(member)
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static inline void psci_dsbish(void)
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{
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dsbish();
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}
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static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
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{
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bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]);
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}
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static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
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{
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bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]);
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}
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#endif /* HW_ASSISTED_COHERENCY */
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static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node,
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unsigned char idx)
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{
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non_cpu_pd_node[idx].lock_index = idx;
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}
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/*******************************************************************************
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* Data prototypes
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******************************************************************************/
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extern const plat_psci_ops_t *psci_plat_pm_ops;
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extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
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extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
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extern unsigned int psci_caps;
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/*******************************************************************************
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* SPD's power management hooks registered with PSCI
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******************************************************************************/
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extern const spd_pm_ops_t *psci_spd_pm;
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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/* Private exported functions from psci_common.c */
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int psci_validate_power_state(unsigned int power_state,
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psci_power_state_t *state_info);
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void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info);
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int psci_validate_mpidr(u_register_t mpidr);
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void psci_init_req_local_pwr_states(void);
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void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
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psci_power_state_t *target_state);
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int psci_validate_entry_point(entry_point_info_t *ep,
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uintptr_t entrypoint, u_register_t context_id);
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void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
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unsigned int end_lvl,
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unsigned int *node_index);
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void psci_do_state_coordination(unsigned int end_pwrlvl,
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psci_power_state_t *state_info);
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void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
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const unsigned int *parent_nodes);
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void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
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const unsigned int *parent_nodes);
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int psci_validate_suspend_req(const psci_power_state_t *state_info,
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unsigned int is_power_down_state);
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unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info);
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unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info);
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void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl);
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void psci_print_power_domain_map(void);
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unsigned int psci_is_last_on_cpu(void);
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int psci_spd_migrate_info(u_register_t *mpidr);
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void psci_do_pwrdown_sequence(unsigned int power_level);
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/*
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* CPU power down is directly called only when HW_ASSISTED_COHERENCY is
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* available. Otherwise, this needs post-call stack maintenance, which is
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* handled in assembly.
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*/
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void prepare_cpu_pwr_dwn(unsigned int power_level);
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/* Private exported functions from psci_on.c */
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int psci_cpu_on_start(u_register_t target_cpu,
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const entry_point_info_t *ep);
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void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info);
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/* Private exported functions from psci_off.c */
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int psci_do_cpu_off(unsigned int end_pwrlvl);
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/* Private exported functions from psci_suspend.c */
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void psci_cpu_suspend_start(const entry_point_info_t *ep,
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unsigned int end_pwrlvl,
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psci_power_state_t *state_info,
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unsigned int is_power_down_state);
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void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info);
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/* Private exported functions from psci_helpers.S */
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void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);
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void psci_do_pwrup_cache_maintenance(void);
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/* Private exported functions from psci_system_off.c */
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void __dead2 psci_system_off(void);
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void __dead2 psci_system_reset(void);
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u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie);
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/* Private exported functions from psci_stat.c */
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void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
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const psci_power_state_t *state_info);
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void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
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const psci_power_state_t *state_info);
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u_register_t psci_stat_residency(u_register_t target_cpu,
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unsigned int power_state);
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u_register_t psci_stat_count(u_register_t target_cpu,
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unsigned int power_state);
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/* Private exported functions from psci_mem_protect.c */
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u_register_t psci_mem_protect(unsigned int enable);
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u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length);
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#endif /* PSCI_PRIVATE_H */
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