71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
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/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* chocodile board configuration */
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#include "adc.h"
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#include "adc_chip.h"
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "host_command.h"
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#include "i2c.h"
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#include "registers.h"
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#include "switch.h"
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#include "system.h"
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#include "task.h"
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#include "usb_pd.h"
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#include "usb_pd_tcpc.h"
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#include "util.h"
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#include "vpd_api.h"
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#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
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void board_config_pre_init(void)
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{
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/* enable SYSCFG clock */
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STM32_RCC_APB2ENR |= 1 << 0;
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}
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#include "gpio_list.h"
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/* Initialize board. */
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static void board_init(void)
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{
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/* Do nothing */
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}
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DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
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/* ADC channels */
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const struct adc_t adc_channels[] = {
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/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
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[ADC_VCONN_VSENSE] = {
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"VCONN_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)},
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[ADC_CC_VPDMCU] = {
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"CC_VPDMCU", 3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)},
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[ADC_CC_RP3A0_RD_L] = {
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"CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)},
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[ADC_RDCONNECT_REF] = {
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"RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)},
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[ADC_CC1_RP3A0_RD_L] = {
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"CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)},
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[ADC_CC2_RP3A0_RD_L] = {
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"CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)},
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[ADC_HOST_VBUS_VSENSE] = {
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"HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)},
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[ADC_CHARGE_VBUS_VSENSE] = {
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"CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)},
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[ADC_CC1_RPUSB_ODH] = {
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"CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)},
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[ADC_CC2_RPUSB_ODH] = {
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"CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)},
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};
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BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
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void tcpc_alert_clear(int port)
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{
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/* Do nothing */
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}
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