150 lines
4.0 KiB
C
150 lines
4.0 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* samus_pd board configuration */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/* 48 MHz SYSCLK clock frequency */
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#define CPU_CLOCK 48000000
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/* the UART console is on USART1 (PA9/PA10) */
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#undef CONFIG_UART_CONSOLE
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#define CONFIG_UART_CONSOLE 1
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/* Optional features */
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#define CONFIG_ADC
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#undef CONFIG_ADC_WATCHDOG
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#define CONFIG_BOARD_PRE_INIT
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#define CONFIG_CHARGE_MANAGER
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#define CONFIG_CHARGE_RAMP_SW
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#undef CONFIG_CMD_ADC
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#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
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#undef CONFIG_CMD_CRASH
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#undef CONFIG_CMD_HASH
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#undef CONFIG_CMD_HCDEBUG
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#undef CONFIG_CMD_I2C_SCAN
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#undef CONFIG_CMD_I2C_XFER
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/* Minimum ilim = 500 mA */
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#define CONFIG_CHARGER_INPUT_CURRENT PWM_0_MA
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#undef CONFIG_CMD_IDLE_STATS
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#undef CONFIG_CMD_MD
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#undef CONFIG_CMD_SHMEM
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#undef CONFIG_CMD_TIMERINFO
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#define CONFIG_COMMON_GPIO_SHORTNAMES
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#undef CONFIG_CONSOLE_CMDHELP
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#undef CONFIG_CONSOLE_HISTORY
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#undef CONFIG_DEBUG_ASSERT
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#define CONFIG_FORCE_CONSOLE_RESUME
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#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP3|STM32_PWR_CSR_EWUP8)
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#define CONFIG_HOSTCMD_ALIGNED
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#undef CONFIG_HOSTCMD_EVENTS
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#define CONFIG_HW_CRC
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#define CONFIG_I2C
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#define CONFIG_I2C_MASTER
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#define CONFIG_I2C_SLAVE
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#undef CONFIG_LID_SWITCH
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#define CONFIG_LOW_POWER_IDLE
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#define CONFIG_LTO
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#undef CONFIG_PWM
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#define CONFIG_STM_HWTIMER32
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#undef CONFIG_TASK_PROFILING
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#define CONFIG_USB_CHARGER
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#define CONFIG_USB_POWER_DELIVERY
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#define CONFIG_USB_PD_ALT_MODE
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#define CONFIG_USB_PD_ALT_MODE_DFP
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#define CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
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#define CONFIG_USB_PD_COMM_LOCKED
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#define CONFIG_USB_PD_DUAL_ROLE
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#define CONFIG_USB_PD_TRY_SRC
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#define CONFIG_USB_PD_FLASH_ERASE_CHECK
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#define CONFIG_USB_PD_INTERNAL_COMP
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#define CONFIG_USB_PD_LOGGING
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#define CONFIG_USB_PD_PORT_COUNT 2
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#define CONFIG_USB_PD_TCPC
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#define CONFIG_USB_PD_TCPM_STUB
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#define CONFIG_USB_PD_VBUS_DETECT_GPIO
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#define CONFIG_BC12_DETECT_PI3USB9281
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#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
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#define CONFIG_USBC_SS_MUX_DFP_ONLY
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#define CONFIG_USBC_SS_MUX
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#define CONFIG_USBC_VCONN
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#define CONFIG_USBC_VCONN_SWAP
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#define CONFIG_VBOOT_HASH
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#undef CONFIG_WATCHDOG_HELP
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/* Use PSTATE embedded in the RO image, not in its own erase block */
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#undef CONFIG_FLASH_PSTATE_BANK
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#undef CONFIG_FW_PSTATE_SIZE
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#define CONFIG_FW_PSTATE_SIZE 0
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/* I2C ports configuration */
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#define I2C_PORT_MASTER 1
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#define I2C_PORT_SLAVE 0
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#define I2C_PORT_EC I2C_PORT_SLAVE
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#define I2C_PORT_PERICOM I2C_PORT_MASTER
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/* slave address for host commands */
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#ifdef HAS_TASK_HOSTCMD
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#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS
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#endif
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#ifndef __ASSEMBLER__
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_ADC 3
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#include "gpio_signal.h"
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/* ADC signal */
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enum adc_channel {
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ADC_C0_CC1_PD = 0,
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ADC_C1_CC1_PD,
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ADC_C0_CC2_PD,
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ADC_C1_CC2_PD,
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ADC_VBUS,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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enum pwm_channel {
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PWM_CH_ILIM = 0,
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/* Number of PWM channels */
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PWM_CH_COUNT
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};
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/* Standard-current Rp */
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#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
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#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
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/*
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* delay to turn on the power supply max is ~16ms.
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* delay to turn off the power supply max is about ~180ms.
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*/
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#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
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#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
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/* delay to turn on/off vconn */
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#define PD_VCONN_SWAP_DELAY 5000 /* us */
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/* Define typical operating power and max power */
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#define PD_OPERATING_POWER_MW 15000
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#define PD_MAX_POWER_MW 60000
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#define PD_MAX_CURRENT_MA 3000
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#define PD_MAX_VOLTAGE_MV 20000
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/* Charge current limit min / max, based on PWM duty cycle */
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#define PWM_0_MA 500
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#define PWM_100_MA 4000
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/* Map current in milli-amps to PWM duty cycle percentage */
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#define MA_TO_PWM(curr) (((curr) - PWM_0_MA) * 100 / (PWM_100_MA - PWM_0_MA))
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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