604 lines
13 KiB
C
604 lines
13 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "adc.h"
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#include "common.h"
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#include "console.h"
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#include "dma.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "injector.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "usb_pd.h"
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#include "usb_pd_config.h"
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#include "util.h"
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#include "watchdog.h"
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/* FSM command/data buffer */
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static uint32_t inj_cmds[INJ_CMD_COUNT];
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/* Current polarity for sending operations */
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static enum inj_pol inj_polarity = INJ_POL_CC1;
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/*
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* CCx Resistors control definition
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*
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* Resistor control GPIOs :
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* CC1_RA A8
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* CC1_RPUSB A13
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* CC1_RP1A5 A14
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* CC1_RP3A0 A15
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* CC2_RPUSB B0
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* CC1_RD B5
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* CC2_RD B8
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* CC2_RA B15
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* CC2_RP1A5 C14
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* CC2_RP3A0 C15
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*/
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static const struct res_cfg {
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const char *name;
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struct config {
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enum gpio_signal signal;
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uint32_t flags;
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} cfgs[2];
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} res_cfg[] = {
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[INJ_RES_NONE] = {"NONE"},
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[INJ_RES_RA] = {"RA", {{GPIO_CC1_RA, GPIO_ODR_LOW},
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{GPIO_CC2_RA, GPIO_ODR_LOW} } },
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[INJ_RES_RD] = {"RD", {{GPIO_CC1_RD, GPIO_ODR_LOW},
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{GPIO_CC2_RD, GPIO_ODR_LOW} } },
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[INJ_RES_RPUSB] = {"RPUSB", {{GPIO_CC1_RPUSB, GPIO_OUT_HIGH},
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{GPIO_CC2_RPUSB, GPIO_OUT_HIGH} } },
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[INJ_RES_RP1A5] = {"RP1A5", {{GPIO_CC1_RP1A5, GPIO_OUT_HIGH},
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{GPIO_CC2_RP1A5, GPIO_OUT_HIGH} } },
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[INJ_RES_RP3A0] = {"RP3A0", {{GPIO_CC1_RP3A0, GPIO_OUT_HIGH},
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{GPIO_CC2_RP3A0, GPIO_OUT_HIGH} } },
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};
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#define CC_RA(cc) (cc < PD_SRC_RD_THRESHOLD)
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#define CC_RD(cc) ((cc > PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
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#define GET_POLARITY(cc1, cc2) (CC_RD(cc2) || CC_RA(cc1))
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#ifdef HAS_TASK_SNIFFER
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/* we don't have the default DMA handlers */
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void dma_event_interrupt_channel_3(void)
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{
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if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH3)) {
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dma_clear_isr(STM32_DMAC_CH3);
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task_wake(TASK_ID_CONSOLE);
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}
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}
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DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_3, 3);
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#endif
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static void twinkie_init(void)
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{
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/* configure TX clock pins */
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gpio_config_module(MODULE_USB_PD, 1);
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/* Initialize physical layer */
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pd_hw_init(0, PD_ROLE_SINK);
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}
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DECLARE_HOOK(HOOK_INIT, twinkie_init, HOOK_PRIO_DEFAULT);
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/* ------ Helper functions ------ */
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static inline int disable_tracing_save(void)
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{
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int tr_enabled = STM32_EXTI_IMR & EXTI_COMP_MASK(0);
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if (tr_enabled)
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pd_rx_disable_monitoring(0);
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return tr_enabled;
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}
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static inline void enable_tracing_ifneeded(int flag)
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{
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if (flag)
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pd_rx_enable_monitoring(0);
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}
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static int send_message(int polarity, uint16_t header,
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uint8_t cnt, const uint32_t *data)
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{
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int bit_len;
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/* Don't get preempted by the tracing */
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int flag = disable_tracing_save();
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bit_len = prepare_message(0, header, cnt, data);
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/* Transmit the packet */
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pd_start_tx(0, polarity, bit_len);
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pd_tx_done(0, polarity);
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enable_tracing_ifneeded(flag);
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return bit_len;
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}
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static int send_hrst(int polarity)
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{
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int off;
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int flag = disable_tracing_save();
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/* 64-bit preamble */
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off = pd_write_preamble(0);
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/* Hard-Reset: 3x RST-1 + 1x RST-2 */
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off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
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off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
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off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
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off = pd_write_sym(0, off, 0b0101001101); /* RST-2 = 11001 */
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/* Ensure that we have a final edge */
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off = pd_write_last_edge(0, off);
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/* Transmit the packet */
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pd_start_tx(0, polarity, off);
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pd_tx_done(0, polarity);
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enable_tracing_ifneeded(flag);
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return off;
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}
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static void set_resistor(int pol, enum inj_res res)
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{
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/* reset everything on one CC to high impedance */
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gpio_set_flags(res_cfg[INJ_RES_RA].cfgs[pol].signal, GPIO_ODR_HIGH);
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gpio_set_flags(res_cfg[INJ_RES_RD].cfgs[pol].signal, GPIO_ODR_HIGH);
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gpio_set_flags(res_cfg[INJ_RES_RPUSB].cfgs[pol].signal, GPIO_ODR_HIGH);
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gpio_set_flags(res_cfg[INJ_RES_RP1A5].cfgs[pol].signal, GPIO_ODR_HIGH);
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gpio_set_flags(res_cfg[INJ_RES_RP3A0].cfgs[pol].signal, GPIO_ODR_HIGH);
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/* connect the resistor if needed */
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if (res != INJ_RES_NONE)
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gpio_set_flags(res_cfg[res].cfgs[pol].signal,
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res_cfg[res].cfgs[pol].flags);
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}
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static enum inj_pol guess_polarity(enum inj_pol pol)
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{
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int cc1_volt, cc2_volt;
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/* polarity forced by the user */
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if (pol == INJ_POL_CC1 || pol == INJ_POL_CC2)
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return pol;
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/* Auto-detection */
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cc1_volt = pd_adc_read(0, 0);
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cc2_volt = pd_adc_read(0, 1);
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return GET_POLARITY(cc1_volt, cc2_volt);
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}
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/* ------ FSM commands ------ */
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static void fsm_send(uint32_t w)
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{
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uint16_t header = INJ_ARG0(w);
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int idx = INJ_ARG1(w);
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uint8_t cnt = INJ_ARG2(w);
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/* Buffer overflow */
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if (idx > INJ_CMD_COUNT)
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return;
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send_message(inj_polarity, header, cnt, inj_cmds + idx);
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}
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static void fsm_wave(uint32_t w)
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{
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uint16_t bit_len = INJ_ARG0(w);
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int idx = INJ_ARG1(w);
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int off = 0;
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int nbwords = DIV_ROUND_UP(bit_len, 32);
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int i;
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int flag;
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/* Buffer overflow */
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if (idx + nbwords > INJ_CMD_COUNT)
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return;
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flag = disable_tracing_save();
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for (i = idx; i < idx + nbwords; i++)
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off = encode_word(0, off, inj_cmds[i]);
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/* Ensure that we have a final edge */
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off = pd_write_last_edge(0, bit_len);
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/* Transmit the packet */
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pd_start_tx(0, inj_polarity, off);
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pd_tx_done(0, inj_polarity);
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enable_tracing_ifneeded(flag);
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}
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static void fsm_wait(uint32_t w)
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{
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#ifdef HAS_TASK_SNIFFER
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uint32_t timeout_ms = INJ_ARG0(w);
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uint32_t min_edges = INJ_ARG12(w);
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wait_packet(inj_polarity, min_edges, timeout_ms * 1000);
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#endif
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}
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static void fsm_expect(uint32_t w)
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{
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uint32_t timeout_ms = INJ_ARG0(w);
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uint8_t cmd = INJ_ARG2(w);
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expect_packet(inj_polarity, cmd, timeout_ms * 1000);
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}
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static void fsm_get(uint32_t w)
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{
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int store_idx = INJ_ARG0(w);
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int param_idx = INJ_ARG1(w);
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uint32_t *store_ptr = inj_cmds + store_idx;
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/* Buffer overflow */
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if (store_idx > INJ_CMD_COUNT)
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return;
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switch (param_idx) {
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case INJ_GET_CC:
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*store_ptr = pd_adc_read(0, 0) | (pd_adc_read(0, 1) << 16);
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break;
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case INJ_GET_VBUS:
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*store_ptr = (ina2xx_get_voltage(0) & 0xffff) |
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((ina2xx_get_current(0) & 0xffff) << 16);
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break;
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case INJ_GET_VCONN:
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*store_ptr = (ina2xx_get_voltage(1) & 0xffff) |
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((ina2xx_get_current(1) & 0xffff) << 16);
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break;
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case INJ_GET_POLARITY:
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*store_ptr = inj_polarity;
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break;
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default:
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/* Do nothing */
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break;
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}
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}
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static void fsm_set(uint32_t w)
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{
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int val = INJ_ARG0(w);
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int idx = INJ_ARG1(w);
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switch (idx) {
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case INJ_SET_RESISTOR1:
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case INJ_SET_RESISTOR2:
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set_resistor(idx - INJ_SET_RESISTOR1, val);
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break;
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case INJ_SET_RECORD:
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#ifdef HAS_TASK_SNIFFER
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recording_enable(val);
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#endif
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break;
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case INJ_SET_TX_SPEED:
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pd_set_clock(0, val * 1000);
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break;
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case INJ_SET_RX_THRESH:
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/* set DAC voltage (Vref = 3.3V) */
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STM32_DAC_DHR12RD = val * 4096 / 3300;
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break;
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case INJ_SET_POLARITY:
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inj_polarity = guess_polarity(val);
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break;
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case INJ_SET_TRACE:
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set_trace_mode(val);
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break;
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default:
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/* Do nothing */
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break;
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}
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}
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static int fsm_run(int index)
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{
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while (index < INJ_CMD_COUNT) {
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uint32_t w = inj_cmds[index];
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int cmd = INJ_CMD(w);
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switch (cmd) {
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case INJ_CMD_END:
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return index;
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case INJ_CMD_SEND:
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fsm_send(w);
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break;
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case INJ_CMD_WAVE:
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fsm_wave(w);
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break;
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case INJ_CMD_HRST:
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send_hrst(inj_polarity);
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break;
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case INJ_CMD_WAIT:
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fsm_wait(w);
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break;
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case INJ_CMD_GET:
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fsm_get(w);
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break;
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case INJ_CMD_SET:
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fsm_set(w);
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break;
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case INJ_CMD_JUMP:
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index = INJ_ARG0(w);
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continue; /* do not increment index */
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case INJ_CMD_EXPCT:
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fsm_expect(w);
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break;
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case INJ_CMD_NOP:
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default:
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/* Do nothing */
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break;
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}
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index += 1;
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watchdog_reload();
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}
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return index;
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}
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/* ------ Console commands ------ */
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static int hex8tou32(char *str, uint32_t *val)
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{
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char *ptr = str;
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uint32_t tmp = 0;
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while (*ptr) {
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char c = *ptr++;
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if (c >= '0' && c <= '9')
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tmp = (tmp << 4) + (c - '0');
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else if (c >= 'A' && c <= 'F')
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tmp = (tmp << 4) + (c - 'A' + 10);
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else if (c >= 'a' && c <= 'f')
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tmp = (tmp << 4) + (c - 'a' + 10);
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else
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return EC_ERROR_INVAL;
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}
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if (ptr != str + 8)
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return EC_ERROR_INVAL;
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*val = tmp;
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return EC_SUCCESS;
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}
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static int cmd_fsm(int argc, char **argv)
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{
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int index;
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char *e;
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if (argc < 1)
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return EC_ERROR_PARAM2;
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index = strtoi(argv[0], &e, 10);
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if (*e)
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return EC_ERROR_PARAM2;
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index = fsm_run(index);
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ccprintf("FSM Done %d\n", index);
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return EC_SUCCESS;
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}
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static int cmd_send(int argc, char **argv)
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{
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int pol, cnt, i;
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uint16_t header;
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uint32_t data[VDO_MAX_SIZE];
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char *e;
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int bit_len;
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cnt = argc - 2;
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if (argc < 2 || cnt > VDO_MAX_SIZE)
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return EC_ERROR_PARAM_COUNT;
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pol = strtoi(argv[0], &e, 10) - 1;
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if (*e || pol > 1 || pol < 0)
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return EC_ERROR_PARAM2;
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header = strtoi(argv[1], &e, 16);
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if (*e)
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return EC_ERROR_PARAM3;
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for (i = 0; i < cnt; i++)
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if (hex8tou32(argv[i+2], data + i))
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return EC_ERROR_INVAL;
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bit_len = send_message(pol, header, cnt, data);
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ccprintf("Sent CC%d %04x + %d = %d\n", pol + 1, header, cnt, bit_len);
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return EC_SUCCESS;
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}
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static int cmd_cc_level(int argc, char **argv)
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{
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ccprintf("CC1 = %d mV ; CC2 = %d mV\n",
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pd_adc_read(0, 0), pd_adc_read(0, 1));
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return EC_SUCCESS;
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}
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static int cmd_resistor(int argc, char **argv)
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{
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int p, r;
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if (argc < 2)
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return EC_ERROR_PARAM_COUNT;
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for (p = 0; p < 2; p++) {
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int is_set = 0;
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for (r = 0; r < ARRAY_SIZE(res_cfg); r++)
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if (strcasecmp(res_cfg[r].name, argv[p]) == 0) {
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set_resistor(p, r);
|
||
|
is_set = 1;
|
||
|
break;
|
||
|
}
|
||
|
/* Unknown name : set to No resistor */
|
||
|
if (!is_set)
|
||
|
set_resistor(p, INJ_RES_NONE);
|
||
|
}
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_tx_clock(int argc, char **argv)
|
||
|
{
|
||
|
int freq;
|
||
|
char *e;
|
||
|
|
||
|
if (argc < 1)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
freq = strtoi(argv[0], &e, 10);
|
||
|
if (*e)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
pd_set_clock(0, freq);
|
||
|
ccprintf("TX frequency = %d Hz\n", freq);
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_rx_threshold(int argc, char **argv)
|
||
|
{
|
||
|
int mv;
|
||
|
char *e;
|
||
|
|
||
|
if (argc < 1)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
mv = strtoi(argv[0], &e, 10);
|
||
|
if (*e)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
/* set DAC voltage (Vref = 3.3V) */
|
||
|
STM32_DAC_DHR12RD = mv * 4096 / 3300;
|
||
|
ccprintf("RX threshold = %d mV\n", mv);
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_ina_dump(int argc, char **argv, int index)
|
||
|
{
|
||
|
if (index == 1) { /* VCONN INA is off by default, switch it on */
|
||
|
ina2xx_write(index, INA2XX_REG_CONFIG, 0x4123);
|
||
|
/*
|
||
|
* wait for the end of conversion : 2x 1.1ms as defined
|
||
|
* by the Vb and Vsh CT bits in the CONFIG register above.
|
||
|
*/
|
||
|
udelay(2200);
|
||
|
}
|
||
|
|
||
|
ccprintf("%s = %d mV ; %d mA\n", index == 0 ? "VBUS" : "VCONN",
|
||
|
ina2xx_get_voltage(index), ina2xx_get_current(index));
|
||
|
|
||
|
if (index == 1) /* power off VCONN INA */
|
||
|
ina2xx_write(index, INA2XX_REG_CONFIG, 0);
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_bufwr(int argc, char **argv)
|
||
|
{
|
||
|
int idx, cnt, i;
|
||
|
char *e;
|
||
|
|
||
|
cnt = argc - 1;
|
||
|
if (argc < 2 || cnt > INJ_CMD_COUNT)
|
||
|
return EC_ERROR_PARAM_COUNT;
|
||
|
|
||
|
idx = strtoi(argv[0], &e, 10);
|
||
|
if (*e || idx + cnt > INJ_CMD_COUNT)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
for (i = 0; i < cnt; i++)
|
||
|
if (hex8tou32(argv[i+1], inj_cmds + idx + i))
|
||
|
return EC_ERROR_INVAL;
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_bufrd(int argc, char **argv)
|
||
|
{
|
||
|
int idx, i;
|
||
|
int cnt = 1;
|
||
|
char *e;
|
||
|
|
||
|
if (argc < 1)
|
||
|
return EC_ERROR_PARAM_COUNT;
|
||
|
|
||
|
idx = strtoi(argv[0], &e, 10);
|
||
|
if (*e || idx > INJ_CMD_COUNT)
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
if (argc >= 2)
|
||
|
cnt = strtoi(argv[1], &e, 10);
|
||
|
|
||
|
if (*e || idx + cnt > INJ_CMD_COUNT)
|
||
|
return EC_ERROR_PARAM3;
|
||
|
|
||
|
for (i = idx; i < idx + cnt; i++)
|
||
|
ccprintf("%08x ", inj_cmds[i]);
|
||
|
ccprintf("\n");
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_sink(int argc, char **argv)
|
||
|
{
|
||
|
/*
|
||
|
* Jump to the RW section which should contain a firmware acting
|
||
|
* as a USB PD sink
|
||
|
*/
|
||
|
system_run_image_copy(SYSTEM_IMAGE_RW);
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int cmd_trace(int argc, char **argv)
|
||
|
{
|
||
|
if (argc < 1)
|
||
|
return EC_ERROR_PARAM_COUNT;
|
||
|
|
||
|
if (!strcasecmp(argv[0], "on") ||
|
||
|
!strcasecmp(argv[0], "1"))
|
||
|
set_trace_mode(TRACE_MODE_ON);
|
||
|
else if (!strcasecmp(argv[0], "raw"))
|
||
|
set_trace_mode(TRACE_MODE_RAW);
|
||
|
else if (!strcasecmp(argv[0], "off") ||
|
||
|
!strcasecmp(argv[0], "0"))
|
||
|
set_trace_mode(TRACE_MODE_OFF);
|
||
|
else
|
||
|
return EC_ERROR_PARAM2;
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
|
||
|
static int command_tw(int argc, char **argv)
|
||
|
{
|
||
|
if (!strcasecmp(argv[1], "send"))
|
||
|
return cmd_send(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "fsm"))
|
||
|
return cmd_fsm(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "bufwr"))
|
||
|
return cmd_bufwr(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "bufrd"))
|
||
|
return cmd_bufrd(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "cc"))
|
||
|
return cmd_cc_level(argc - 2, argv + 2);
|
||
|
else if (!strncasecmp(argv[1], "resistor", 3))
|
||
|
return cmd_resistor(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "sink"))
|
||
|
return cmd_sink(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "trace"))
|
||
|
return cmd_trace(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "txclock"))
|
||
|
return cmd_tx_clock(argc - 2, argv + 2);
|
||
|
else if (!strncasecmp(argv[1], "rxthresh", 8))
|
||
|
return cmd_rx_threshold(argc - 2, argv + 2);
|
||
|
else if (!strcasecmp(argv[1], "vbus"))
|
||
|
return cmd_ina_dump(argc - 2, argv + 2, 0);
|
||
|
else if (!strcasecmp(argv[1], "vconn"))
|
||
|
return cmd_ina_dump(argc - 2, argv + 2, 1);
|
||
|
else
|
||
|
return EC_ERROR_PARAM1;
|
||
|
|
||
|
return EC_SUCCESS;
|
||
|
}
|
||
|
DECLARE_CONSOLE_COMMAND(twinkie, command_tw,
|
||
|
"[send|fsm|cc|resistor|txclock|rxthresh|vbus|vconn]",
|
||
|
"Manual Twinkie tweaking");
|