189 lines
8.6 KiB
PHP
189 lines
8.6 KiB
PHP
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/* -*- mode:c -*-
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*
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* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Declare symbolic names for all the GPIOs that we care about.
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* Note: Those with interrupt handlers must be declared first. */
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/* Wake Source interrupts */
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GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH |
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GPIO_HIB_WAKE_HIGH, lid_interrupt)
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/*
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* High-to-low transition on POWER_BUTTON_L is treated as a wake event from
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* hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
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* high-to-low edge.
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*/
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GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */
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GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH |
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GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* ACOK_OD */
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/* USB-C interrupts */
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GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
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GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
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GPIO_INT(USB_PD_C0_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
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GPIO_INT(USB_PD_C1_INT_ODL, PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
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/* Power State interrupts */
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#ifdef CONFIG_POWER_S0IX
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GPIO_INT(PCH_SLP_S0_L, PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
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#endif
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GPIO_INT(PCH_SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */
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GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */
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GPIO_INT(SUSPWRDNACK, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRDNACK */
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GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */
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GPIO_INT(ALL_SYS_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */
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/* Other interrupts */
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GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */
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GPIO_INT(TABLET_MODE_L, PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
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GPIO_INT(BASE_SIXAXIS_INT_L, PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
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GPIO(LID_ACCEL_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
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/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
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#ifndef CONFIG_POWER_S0IX
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GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
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#endif
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/*
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* PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
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* only for debugging purposes.
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*/
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GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
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GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
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GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
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GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
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GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
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GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */
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GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW) /* EN_PP5000_A */
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GPIO(PP5000_PG, PIN(C, 0), GPIO_INPUT) /* PP5000_PG_OD */
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GPIO(EN_PP3300, PIN(D, 4), GPIO_OUT_LOW) /* EN_PP3300_A */
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GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */
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GPIO(PMIC_EN, PIN(7, 2), GPIO_OUT_LOW) /* Enable A Rails via PMIC */
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GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */
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GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */
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/* Peripheral rails */
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GPIO(ENABLE_BACKLIGHT, PIN(D, 3), GPIO_ODR_HIGH |
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GPIO_SEL_1P8V) /* EC_BL_EN_OD */
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GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 3), GPIO_ODR_HIGH)
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GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT)
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/*
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* EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
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* not need to be an interrupt for normal EC operations. Thus, configure it as
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* GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
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* common code can configure PSL_IN correctly.
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*
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* Reason for choosing low-to-high edge for waking from hibernate is to avoid
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* the double reset - one because of PSL_IN wake and other because of VCC1_RST
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* being asserted. Also, it should be fine to have the EC in hibernate when H1
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* or servo wants to hold the EC in reset since VCC1 will be down and so entire
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* EC logic (except PSL) as well as AP will be in reset.
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*/
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GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
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/*
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* PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
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* normally driven by the PMIC. The EC can also drive this signal in the event
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* that the ambient or charger temperature sensors exceeds their thresholds.
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*/
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GPIO(CPU_PROCHOT, PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */
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/* I2C pins - Alternate function below configures I2C module on these pins */
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GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SCL */
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GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SDA */
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GPIO(I2C1_SCL, PIN(9, 0), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SCL */
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GPIO(I2C1_SDA, PIN(8, 7), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SDA */
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GPIO(I2C2_SCL, PIN(9, 2), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SCL */
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GPIO(I2C2_SDA, PIN(9, 1), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SDA */
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GPIO(I2C3_SCL, PIN(D, 1), GPIO_INPUT) /* EC_I2C_EEPROM_SCL */
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GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT) /* EC_I2C_EEPROM_SDA */
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GPIO(I2C4_SCL, PIN(F, 3), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SCL */
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GPIO(I2C4_SDA, PIN(F, 2), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SDA */
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GPIO(I2C7_SCL, PIN(B, 3), GPIO_INPUT |
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GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SCL */
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GPIO(I2C7_SDA, PIN(B, 2), GPIO_INPUT |
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GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SDA */
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/* USB pins */
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GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */
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GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */
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GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */
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GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */
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GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */
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GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */
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GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */
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GPIO_SEL_1P8V)
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GPIO(USB_C1_PD_RST_ODL, PIN(7, 0), GPIO_ODR_HIGH) /* C1 PD Reset */
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GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */
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GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */
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GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */
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GPIO_SEL_1P8V)
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/* Not implemented in hardware */
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UNIMPLEMENTED(USB_C0_PD_RST)
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/*
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* USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it
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* 3.3V on the EC side. So, configure it as ODR so that the EC never drives it
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* high.
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*/
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GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_ODR_LOW) /* OTG ID */
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/* LED */
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GPIO(BAT_LED_ORANGE_L, PIN(C, 3), GPIO_OUT_HIGH) /* LED_1_L */
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GPIO(BAT_LED_BLUE_L, PIN(C, 4), GPIO_OUT_HIGH) /* LED_2_L */
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GPIO(LED_3_L, PIN(D, 7), GPIO_OUT_HIGH)
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/* Keyboard Backlight */
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GPIO(KB_BL_PWR_EN, PIN(6, 2), GPIO_OUT_LOW)
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/* Camera */
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GPIO(WFCAM_VSYNC, PIN(0, 3), GPIO_INPUT) /* TP only */
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/* MKBP event synchronization */
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GPIO(EC_INT_L, PIN(9, 4), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
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/* Overcurrent event to host */
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GPIO(USB_C_OC, PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
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/* Strap pins */
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GPIO(GPO66_NC, PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
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GPIO(GPOB6_NC, PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
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/* Misc. */
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GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT)
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/* Keyboard pins */
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ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */
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ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */
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ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
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ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
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ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-12 */
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GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */
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/* Alternate functions GPIO definitions */
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/* Cr50 requires no pull-ups on UART pins. */
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ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* UART from EC to Servo */
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ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */
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ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */
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ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */
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ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* I2C3 */
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ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */
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ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
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ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */
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ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* KB_BL_PWM */
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/* Power Switch Logic (PSL) inputs */
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ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 = LID_OPEN */
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ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD,
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GPIO01 = MECH_PWR_BTN_ODL
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GPIO02 = EC_RST_ODL */
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