121 lines
3.6 KiB
C
121 lines
3.6 KiB
C
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/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Watchdog driver */
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#include "clock.h"
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#include "common.h"
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#include "registers.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "task.h"
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#include "util.h"
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#include "watchdog.h"
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/*
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* We use watchdog 0 which is clocked on the system clock
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* to avoid the penalty cycles on each write access
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*/
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/* magic value to unlock the watchdog registers */
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#define LM4_WATCHDOG_MAGIC_WORD 0x1ACCE551
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static uint32_t watchdog_period; /* Watchdog counter initial value */
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void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) __attribute__((naked));
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void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void)
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{
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/* Naked call so we can extract raw LR and SP */
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asm volatile("mov r0, lr\n"
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"mov r1, sp\n"
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/* Must push registers in pairs to keep 64-bit aligned
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* stack for ARM EABI. This also conveniently saves
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* R0=LR so we can pass it to task_resched_if_needed. */
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"push {r0, lr}\n"
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"bl watchdog_trace\n"
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/* Do NOT reset the watchdog interrupt here; it will
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* be done in watchdog_reload(), or reset will be
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* triggered if we don't call that by the next watchdog
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* period. Instead, de-activate the interrupt in the
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* NVIC, so the watchdog trace will only be printed
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* once.
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*/
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"mov r0, %[irq]\n"
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"bl task_disable_irq\n"
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"pop {r0, lr}\n"
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"b task_resched_if_needed\n"
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: : [irq] "i" (LM4_IRQ_WATCHDOG));
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}
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const struct irq_priority __keep IRQ_PRIORITY(LM4_IRQ_WATCHDOG)
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__attribute__((section(".rodata.irqprio")))
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= {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest
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priority */
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void watchdog_reload(void)
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{
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uint32_t status = LM4_WATCHDOG_RIS(0);
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/* Unlock watchdog registers */
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LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
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/* As we reboot only on the second timeout, if we have already reached
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* the first timeout we need to reset the interrupt bit. */
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if (status) {
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LM4_WATCHDOG_ICR(0) = status;
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/* That doesn't seem to unpend the watchdog interrupt (even if
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* we do dummy writes to force the write to be committed), so
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* explicitly unpend the interrupt before re-enabling it. */
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task_clear_pending_irq(LM4_IRQ_WATCHDOG);
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task_enable_irq(LM4_IRQ_WATCHDOG);
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}
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/* Reload the watchdog counter */
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LM4_WATCHDOG_LOAD(0) = watchdog_period;
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/* Re-lock watchdog registers */
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LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
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}
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DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
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static void watchdog_freq_changed(void)
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{
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/* Set the timeout period */
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watchdog_period = CONFIG_WATCHDOG_PERIOD_MS * (clock_get_freq() / 1000);
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/* Reload the watchdog timer now */
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watchdog_reload();
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, watchdog_freq_changed, HOOK_PRIO_DEFAULT);
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int watchdog_init(void)
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{
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/* Enable watchdog 0 clock in run, sleep, and deep sleep modes */
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clock_enable_peripheral(CGC_OFFSET_WD, 0x1, CGC_MODE_ALL);
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/* Set initial timeout period */
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watchdog_freq_changed();
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/* Unlock watchdog registers */
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LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
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/* De-activate the watchdog when the JTAG stops the CPU */
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LM4_WATCHDOG_TEST(0) |= BIT(8);
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/* Reset after 2 time-out, activate the watchdog and lock the control
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* register. */
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LM4_WATCHDOG_CTL(0) = 0x3;
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/* Reset watchdog interrupt bits */
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LM4_WATCHDOG_ICR(0) = LM4_WATCHDOG_RIS(0);
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/* Lock watchdog registers against unintended accesses */
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LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
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/* Enable watchdog interrupt */
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task_enable_irq(LM4_IRQ_WATCHDOG);
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return EC_SUCCESS;
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}
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