144 lines
6.0 KiB
C
144 lines
6.0 KiB
C
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/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MAX32660 Registers, Bit Masks and Bit Positions for the ICC */
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#ifndef _ICC_REGS_H_
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#define _ICC_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/**
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* Structure type to access the ICC Registers.
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*/
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typedef struct {
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__I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */
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__I uint32_t memcfg; /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
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__R uint32_t rsv_0x8_0xff[62];
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__IO uint32_t
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cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */
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__R uint32_t rsv_0x104_0x6ff[383];
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__IO uint32_t
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invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */
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} mxc_icc_regs_t;
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/**
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* ICC Peripheral Register Offsets from the ICC Base Peripheral
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* Address.
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*/
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#define MXC_R_ICC_CACHE_ID \
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((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> \
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0x0x000 */
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#define MXC_R_ICC_MEMCFG \
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((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> \
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0x0x004 */
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#define MXC_R_ICC_CACHE_CTRL \
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((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> \
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0x0x100 */
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#define MXC_R_ICC_INVALIDATE \
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((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> \
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0x0x700 */
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/**
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* Cache ID Register.
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*/
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#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
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#define MXC_F_ICC_CACHE_ID_RELNUM \
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((uint32_t)( \
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0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
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Mask */
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#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
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#define MXC_F_ICC_CACHE_ID_PARTNUM \
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((uint32_t)(0xFUL \
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<< MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \
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Mask */
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#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
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#define MXC_F_ICC_CACHE_ID_CCHID \
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((uint32_t)( \
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0x3FUL \
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<< MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
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/**
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* Memory Configuration Register.
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*/
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#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
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#define MXC_F_ICC_MEMCFG_CCHSZ \
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((uint32_t)(0xFFFFUL \
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<< MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
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#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
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#define MXC_F_ICC_MEMCFG_MEMSZ \
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((uint32_t)(0xFFFFUL \
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<< MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
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/**
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* Cache Control and Status Register.
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*/
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#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS \
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0 /**< CACHE_CTRL_CACHE_EN Position \
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*/
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#define MXC_F_ICC_CACHE_CTRL_CACHE_EN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< \
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CACHE_CTRL_CACHE_EN \
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Mask */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \
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((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS \
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(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \
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Setting */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \
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((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN \
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(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \
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Setting */
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#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \
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16 /**< CACHE_CTRL_CACHE_RDY Position */
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#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< \
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CACHE_CTRL_CACHE_RDY \
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Mask */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \
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((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \
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(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \
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CACHE_CTRL_CACHE_RDY_NOTREADY \
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Setting */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \
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((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY \
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(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \
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<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \
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CACHE_CTRL_CACHE_RDY_READY \
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Setting */
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#endif /* _ICC_REGS_H_ */
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