434 lines
11 KiB
C
434 lines
11 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* GPIO module for MCHP MEC */
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "lpc_chip.h"
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#include "tfdp_chip.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_LPC, outstr)
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#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
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struct gpio_int_mapping {
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int8_t girq_id;
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int8_t port_offset;
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};
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/*
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* Mapping from GPIO port to GIRQ info
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* MEC17xx each bank contains 32 GPIO's.
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* Pin Id is the bit position [0:31]
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* Bank GPIO's GIRQ
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* 0 0000 - 0036 11
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* 1 0040 - 0076 10
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* 2 0100 - 0135 9
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* 3 0140 - 0175 8
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* 4 0200 - 0235 12
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* 5 0240 - 0276 26
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*/
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static const struct gpio_int_mapping int_map[6] = {
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{ 11, 0 }, { 10, 1 }, { 9, 2 },
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{ 8, 3 }, { 12, 4 }, { 26, 5 }
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};
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/*
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* NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant
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* 1-bit of val or if val == 0 returns 0
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*/
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void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
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{
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int i;
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uint32_t val;
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while (mask) {
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i = __builtin_ffs(mask) - 1;
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val = MCHP_GPIO_CTL(port, i);
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val &= ~(BIT(12) | BIT(13));
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/* mux_control = 0 indicates GPIO */
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if (func > 0)
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val |= (func & 0x3) << 12;
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MCHP_GPIO_CTL(port, i) = val;
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mask &= ~BIT(i);
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}
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}
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test_mockable int gpio_get_level(enum gpio_signal signal)
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{
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uint32_t mask = gpio_list[signal].mask;
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int i;
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uint32_t val;
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if (mask == 0)
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return 0;
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i = GPIO_MASK_TO_NUM(mask);
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val = MCHP_GPIO_CTL(gpio_list[signal].port, i);
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return (val & BIT(24)) ? 1 : 0;
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}
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void gpio_set_level(enum gpio_signal signal, int value)
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{
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uint32_t mask = gpio_list[signal].mask;
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int i;
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if (mask == 0)
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return;
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i = GPIO_MASK_TO_NUM(mask);
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if (value)
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MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
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else
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MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
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}
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/*
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* Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN.
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* If GPIO_POWER_DONW flag is set force GPIO Control to
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* GPIO input, interrupt detect disabled, power control field
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* in bits[3:2]=10b.
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* NOTE: if interrupt detect is enabled when pin is powered down
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* then a false edge may be detected.
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*
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*/
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void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
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{
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int i;
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uint32_t val;
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while (mask) {
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i = GPIO_MASK_TO_NUM(mask);
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mask &= ~BIT(i);
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val = MCHP_GPIO_CTL(port, i);
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#ifdef CONFIG_GPIO_POWER_DOWN
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if (flags & GPIO_POWER_DOWN) {
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val = (MCHP_GPIO_CTRL_PWR_OFF +
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MCHP_GPIO_INTDET_DISABLED);
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MCHP_GPIO_CTL(port, i) = val;
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continue;
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}
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#endif
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val &= ~(MCHP_GPIO_CTRL_PWR_MASK);
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val |= MCHP_GPIO_CTRL_PWR_VTR;
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/*
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* Select open drain first, so that we don't
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* glitch the signal when changing the line to
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* an output.
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*/
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if (flags & GPIO_OPEN_DRAIN)
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val |= (MCHP_GPIO_OPEN_DRAIN);
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else
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val &= ~(MCHP_GPIO_OPEN_DRAIN);
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if (flags & GPIO_OUTPUT) {
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val |= (MCHP_GPIO_OUTPUT);
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val &= ~(MCHP_GPIO_OUTSEL_PAR);
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} else {
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val &= ~(MCHP_GPIO_OUTPUT);
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val |= (MCHP_GPIO_OUTSEL_PAR);
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}
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/* Handle pull-up / pull-down */
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val &= ~(MCHP_GPIO_CTRL_PUD_MASK);
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if (flags & GPIO_PULL_UP)
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val |= MCHP_GPIO_CTRL_PUD_PU;
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else if (flags & GPIO_PULL_DOWN)
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val |= MCHP_GPIO_CTRL_PUD_PD;
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else
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val |= MCHP_GPIO_CTRL_PUD_NONE;
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/* Set up interrupt */
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val &= ~(MCHP_GPIO_INTDET_MASK);
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switch (flags & GPIO_INT_ANY) {
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case GPIO_INT_F_RISING:
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val |= MCHP_GPIO_INTDET_EDGE_RIS;
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break;
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case GPIO_INT_F_FALLING:
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val |= MCHP_GPIO_INTDET_EDGE_FALL;
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break;
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case GPIO_INT_BOTH: /* both edges */
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val |= MCHP_GPIO_INTDET_EDGE_BOTH;
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break;
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case GPIO_INT_F_LOW:
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val |= MCHP_GPIO_INTDET_LVL_LO;
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break;
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case GPIO_INT_F_HIGH:
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val |= MCHP_GPIO_INTDET_LVL_HI;
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break;
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default:
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val |= MCHP_GPIO_INTDET_DISABLED;
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break;
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}
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/* Set up level */
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if (flags & GPIO_HIGH)
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val |= (MCHP_GPIO_CTRL_OUT_LVL);
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else if (flags & GPIO_LOW)
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val &= ~(MCHP_GPIO_CTRL_OUT_LVL);
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MCHP_GPIO_CTL(port, i) = val;
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}
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}
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void gpio_power_off_by_mask(uint32_t port, uint32_t mask)
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{
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int i;
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while (mask) {
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i = GPIO_MASK_TO_NUM(mask);
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mask &= ~BIT(i);
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MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF +
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MCHP_GPIO_INTDET_DISABLED);
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}
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}
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int gpio_power_off(enum gpio_signal signal)
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{
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int i, port;
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if (gpio_list[signal].mask == 0)
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return EC_ERROR_INVAL;
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i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
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port = gpio_list[signal].port;
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MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF +
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MCHP_GPIO_INTDET_DISABLED);
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return EC_SUCCESS;
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}
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/*
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* gpio_list[signal].port = [0, 6] each port contains up to 32 pins
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* gpio_list[signal].mask = bit mask in 32-bit port
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* NOTE: MCHP GPIO are always aggregated not direct connected to NVIC.
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* GPIO's are aggregated into banks of 32 pins.
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* Each bank/port are connected to a GIRQ.
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* int_map[port].girq_id is the GIRQ ID
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* The bit number in the GIRQ registers is the same as the bit number
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* in the GPIO bank.
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*/
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int gpio_enable_interrupt(enum gpio_signal signal)
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{
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int i, port, girq_id;
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if (gpio_list[signal].mask == 0)
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return EC_SUCCESS;
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i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
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port = gpio_list[signal].port;
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girq_id = int_map[port].girq_id;
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MCHP_INT_ENABLE(girq_id) = BIT(i);
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MCHP_INT_BLK_EN |= BIT(girq_id);
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return EC_SUCCESS;
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}
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int gpio_disable_interrupt(enum gpio_signal signal)
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{
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int i, port, girq_id;
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if (gpio_list[signal].mask == 0)
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return EC_SUCCESS;
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i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
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port = gpio_list[signal].port;
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girq_id = int_map[port].girq_id;
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MCHP_INT_DISABLE(girq_id) = BIT(i);
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return EC_SUCCESS;
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}
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/*
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* MCHP Interrupt Source is R/W1C no need for read-modify-write.
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* GPIO's are aggregated meaning the NVIC Pending bit may be
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* set for another GPIO in the GIRQ. You can clear NVIC pending
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* and the hardware should re-assert it within one Cortex-M4 clock.
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* If the Cortex-M4 is clocked slower than AHB then the Cortex-M4
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* will take longer to register the interrupt. Not clearing NVIC
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* pending leave a pending status if only the GPIO this routine
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* clears is pending.
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* NVIC (system control) register space is strongly-ordered
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* Interrupt Aggregator is in Device space (system bus connected
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* to AHB) with the Cortex-M4 write buffer.
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* We need to insure the write to aggregator register in device
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* AHB space completes before NVIC pending is cleared.
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* The Cortex-M4 memory ordering rules imply Device access
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* comes before strongly ordered access. Cortex-M4 will not re-order
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* the writes. Due to the presence of the write buffer a DSB will
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* not guarantee the clearing of the device status completes. Add
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* a read back before clearing NVIC pending.
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* GIRQ 8, 9, 10, 11, 12, 26 map to NVIC inputs 0, 1, 2, 3, 4, and 18.
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*/
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int gpio_clear_pending_interrupt(enum gpio_signal signal)
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{
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int i, port, girq_id;
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if (gpio_list[signal].mask == 0)
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return EC_SUCCESS;
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i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
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port = gpio_list[signal].port;
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girq_id = int_map[port].girq_id;
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/* Clear interrupt source sticky status bit even if not enabled */
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MCHP_INT_SOURCE(girq_id) = BIT(i);
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i = MCHP_INT_SOURCE(girq_id);
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task_clear_pending_irq(girq_id - 8);
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return EC_SUCCESS;
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}
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/*
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* MCHP NOTE - called from main before scheduler started
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*/
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void gpio_pre_init(void)
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{
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int i;
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int flags;
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int is_warm = system_is_reboot_warm();
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const struct gpio_info *g = gpio_list;
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for (i = 0; i < GPIO_COUNT; i++, g++) {
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flags = g->flags;
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if (flags & GPIO_DEFAULT)
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continue;
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/*
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* If this is a warm reboot, don't set the output levels or
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* we'll shut off the AP.
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*/
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if (is_warm)
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flags &= ~(GPIO_LOW | GPIO_HIGH);
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gpio_set_flags_by_mask(g->port, g->mask, flags);
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/* Use as GPIO, not alternate function */
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gpio_set_alternate_function(g->port, g->mask, -1);
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}
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}
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/* Clear any interrupt flags before enabling GPIO interrupt
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* Original code has flaws.
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* Writing result register to source only clears bits that have their
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* enable and sources bits set.
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* We must clear the NVIC pending R/W bit before setting NVIC enable.
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* NVIC Pending is only cleared by the NVIC HW on ISR entry.
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* Modifications are:
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* 1. Clear all status bits in each GPIO GIRQ. This assumes any edges
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* will occur after gpio_init. The old code is also making this
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* assumption for the GPIO's that have been enabled.
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* 2. Clear NVIC pending to prevent ISR firing on false edge.
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*/
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#define ENABLE_GPIO_GIRQ(x) \
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do { \
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MCHP_INT_SOURCE(x) = 0xfffffffful; \
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task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \
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task_enable_irq(MCHP_IRQ_GIRQ ## x); \
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} while (0)
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static void gpio_init(void)
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{
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ENABLE_GPIO_GIRQ(8);
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ENABLE_GPIO_GIRQ(9);
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ENABLE_GPIO_GIRQ(10);
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ENABLE_GPIO_GIRQ(11);
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ENABLE_GPIO_GIRQ(12);
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ENABLE_GPIO_GIRQ(26);
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}
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DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
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/************************************************************************/
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/* Interrupt handlers */
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/**
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* Handler for each GIRQ interrupt. This reads and clears the interrupt
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* bits for the GIRQ interrupt, then finds and calls the corresponding
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* GPIO interrupt handlers.
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*
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* @param girq GIRQ index
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* @param port zero based GPIO port number [0, 5]
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* @note __builtin_ffs(x) returns bitpos+1 of least significant 1-bit
|
||
|
|
* in x or 0 if no bits are set.
|
||
|
|
*/
|
||
|
|
static void gpio_interrupt(int girq, int port)
|
||
|
|
{
|
||
|
|
int i, bit;
|
||
|
|
const struct gpio_info *g = gpio_list;
|
||
|
|
uint32_t sts = MCHP_INT_RESULT(girq);
|
||
|
|
|
||
|
|
/* RW1C, no need for read-modify-write */
|
||
|
|
MCHP_INT_SOURCE(girq) = sts;
|
||
|
|
|
||
|
|
trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts);
|
||
|
|
trace12(0, GPIO, 0, "GPIO ParIn[%d] = 0x%08x",
|
||
|
|
port, MCHP_GPIO_PARIN(port));
|
||
|
|
|
||
|
|
for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) {
|
||
|
|
if (g->port != port)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
bit = __builtin_ffs(g->mask);
|
||
|
|
if (bit) {
|
||
|
|
bit--;
|
||
|
|
if (sts & BIT(bit)) {
|
||
|
|
trace12(0, GPIO, 0,
|
||
|
|
"Bit[%d]: handler @ 0x%08x", bit,
|
||
|
|
(uint32_t)gpio_irq_handlers[i]);
|
||
|
|
gpio_irq_handlers[i](i);
|
||
|
|
}
|
||
|
|
sts &= ~BIT(bit);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GPIO_IRQ_FUNC(irqfunc, girq, port)\
|
||
|
|
void irqfunc(void) \
|
||
|
|
{ \
|
||
|
|
gpio_interrupt(girq, port);\
|
||
|
|
}
|
||
|
|
|
||
|
|
GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3);
|
||
|
|
GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 2);
|
||
|
|
GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 1);
|
||
|
|
GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
|
||
|
|
GPIO_IRQ_FUNC(__girq_12_interrupt, 12, 4);
|
||
|
|
GPIO_IRQ_FUNC(__girq_26_interrupt, 26, 5);
|
||
|
|
|
||
|
|
#undef GPIO_IRQ_FUNC
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Declare IRQs. Nesting this macro inside the GPIO_IRQ_FUNC macro works
|
||
|
|
* poorly because DECLARE_IRQ() stringizes its inputs.
|
||
|
|
*/
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ8, __girq_8_interrupt, 1);
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ9, __girq_9_interrupt, 1);
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ10, __girq_10_interrupt, 1);
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ11, __girq_11_interrupt, 1);
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ12, __girq_12_interrupt, 1);
|
||
|
|
DECLARE_IRQ(MCHP_IRQ_GIRQ26, __girq_26_interrupt, 1);
|
||
|
|
|