52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Port 80 Timer Interrupt for MCHP MEC family */
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#include "common.h"
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#include "console.h"
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#include "hooks.h"
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#include "lpc.h"
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#include "port80.h"
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#include "registers.h"
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#include "task.h"
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#include "tfdp_chip.h"
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/*
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* Interrupt fires when number of bytes written
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* to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level
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* Issues:
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* 1. eSPI will not break 16-bit I/O into two 8-bit writes
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* as LPC does. This means Port80 hardware will capture
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* only bits[7:0] of data.
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* 2. If Host performs write of 16-bit code as consecutive
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* byte writes the Port80 hardware will capture both but
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* we do not know the order it was written.
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* 3. If Host sometimes writes one byte code to I/O 80h and
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* sometimes two byte code to I/O 80h/81h how do we determine
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* what to do?
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*
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* An alternative is to document Host must write 16-bit codes
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* to I/O 80h and 90h. LSB to 0x80 and MSB to 0x90.
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*
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*/
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void port_80_interrupt(void)
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{
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int d;
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while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) {
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/* this masks off time stamp d = port_80_read(); */
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d = MCHP_P80_CAP(0); /* b[7:0] = data, b[31:8] = timestamp */
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trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff));
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port_80_write(d & 0xff);
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}
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MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0);
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}
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DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3);
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