323 lines
8.7 KiB
C
323 lines
8.7 KiB
C
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/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* SCP memory map
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*/
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#include "common.h"
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#include "compile_time_macros.h"
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#include "console.h"
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#include "hooks.h"
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#include "memmap.h"
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#include "registers.h"
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#include "util.h"
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/*
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* Map SCP address (bits 31~28) to AP address
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*
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* SCP addr : AP addr
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* 0x20000000 0x40000000
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* 0x30000000 0x50000000
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* 0x60000000 0x60000000
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* 0x70000000 0x70000000
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* 0x80000000 0x80000000
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* 0x90000000 0x00000000
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* 0xA0000000 0x10000000
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* 0xB0000000 0x20000000
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* 0xC0000000 0x30000000
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* 0xD0000000 0x10000000
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* 0xE0000000 0xA0000000
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* 0xF0000000 0x90000000
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*/
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#define MAP_INVALID 0xff
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static const uint8_t addr_map[16] = {
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MAP_INVALID, /* 0x0: SRAM */
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MAP_INVALID, /* 0x1: Cached access (see below) */
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0x4, 0x5, /* 0x2-0x3 */
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MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */
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0x6, 0x7, 0x8, /* 0x6-0x8 */
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0x0, 0x1, 0x2, 0x3, /* 0x9-0xc */
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0x1, 0xa, 0x9 /* 0xd-0xf */
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};
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/*
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* AP addr : SCP cache addr
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* 0x50000000 0x10000000
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*/
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#define CACHE_TRANS_AP_ADDR 0x50000000
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#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
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/* FIXME: This should be configurable */
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#define CACHE_TRANS_AP_SIZE 0x00400000
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#ifdef CONFIG_DRAM_BASE
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BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
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BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
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#endif
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static void cpu_invalidate_icache(void)
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{
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SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
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SCP_CACHE_OP(CACHE_ICACHE) |=
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OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
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asm volatile("dsb; isb");
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}
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void cpu_invalidate_dcache(void)
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{
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SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
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/* Dummy read is necessary to confirm the invalidation finish. */
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REG32(CACHE_TRANS_SCP_CACHE_ADDR);
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asm volatile("dsb;");
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}
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void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
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{
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size_t pos;
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uintptr_t addr;
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for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
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addr = base + pos;
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SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
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/* Dummy read necessary to confirm the invalidation finish. */
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REG32(addr);
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}
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asm volatile("dsb;");
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}
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void cpu_clean_invalidate_dcache(void)
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{
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SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN;
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SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
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/* Dummy read necessary to confirm the invalidation finish. */
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REG32(CACHE_TRANS_SCP_CACHE_ADDR);
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asm volatile("dsb;");
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}
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void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
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{
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size_t pos;
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uintptr_t addr;
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for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
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addr = base + pos;
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SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
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SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
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SCP_CACHE_OP(CACHE_DCACHE) |=
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OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
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/* Dummy read necessary to confirm the invalidation finish. */
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REG32(addr);
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}
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asm volatile("dsb;");
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}
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static void scp_cache_init(void)
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{
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int c;
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const int region = 0;
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/* First make sure all caches are disabled, and reset stats. */
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for (c = 0; c < CACHE_COUNT; c++) {
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/*
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* Changing cache-size config may change the SRAM logical
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* address in the mean time. This may break the loaded
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* memory layout, and thus break the system. Cache-size
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* should only be be configured in kernel driver before
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* laoding the firmware. b/137920815#comment18
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*/
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SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK |
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SCP_CACHE_CON_WAYEN);
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SCP_CACHE_REGION_EN(c) = 0;
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SCP_CACHE_ENTRY(c, region) = 0;
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SCP_CACHE_END_ENTRY(c, region) = 0;
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/* Reset statistics. */
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SCP_CACHE_HCNT0U(c) = 0;
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SCP_CACHE_HCNT0L(c) = 0;
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SCP_CACHE_CCNT0U(c) = 0;
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SCP_CACHE_CCNT0L(c) = 0;
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}
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/* No "normal" remap. */
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SCP_L1_REMAP_CFG0 = 0;
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SCP_L1_REMAP_CFG1 = 0;
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SCP_L1_REMAP_CFG2 = 0;
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SCP_L1_REMAP_CFG3 = 0;
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/*
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* Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and
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* not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7.
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*/
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SCP_L1_REMAP_OTHER =
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(CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8;
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/* Disable sleep protect */
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SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
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~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
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/* Enable region 0 for both I-cache and D-cache. */
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for (c = 0; c < CACHE_COUNT; c++) {
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SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR;
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SCP_CACHE_END_ENTRY(c, region) =
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CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE;
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SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C;
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SCP_CACHE_REGION_EN(c) |= 1 << region;
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/*
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* Enable cache. Note that cache size setting should have been
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* done in kernel driver. b/137920815#comment18
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*/
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SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0;
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}
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cpu_invalidate_icache();
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cpu_invalidate_dcache();
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}
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static int command_cacheinfo(int argc, char **argv)
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{
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const char cache_name[] = {'I', 'D'};
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int c;
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for (c = 0; c < 2; c++) {
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uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
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SCP_CACHE_HCNT0L(c);
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uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
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SCP_CACHE_CCNT0L(c);
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ccprintf("%ccache hit count: %lu\n", cache_name[c], hit);
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ccprintf("%ccache access count: %lu\n", cache_name[c], access);
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}
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return EC_SUCCESS;
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}
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DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo,
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NULL,
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"Dump cache info");
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void scp_memmap_init(void)
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{
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/*
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* Default config, LARGE DRAM not active:
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* REG32(0xA0001F00) & 0x2000 != 0
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*/
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/*
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* SCP_REMAP_CFG1
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* EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
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* EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
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* EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3
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* EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2
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*/
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SCP_REMAP_CFG1 =
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(uint32_t)addr_map[0x7] << 24 |
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(uint32_t)addr_map[0x6] << 16 |
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(uint32_t)addr_map[0x3] << 8 |
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(uint32_t)addr_map[0x2];
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/*
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* SCP_REMAP_CFG2
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* EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
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* EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
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* EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9
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* EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8
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*/
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SCP_REMAP_CFG2 =
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(uint32_t)addr_map[0xb] << 24 |
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(uint32_t)addr_map[0xa] << 16 |
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(uint32_t)addr_map[0x9] << 8 |
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(uint32_t)addr_map[0x8];
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/*
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* SCP_REMAP_CFG3
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* AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd
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* EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
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* EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe
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* EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc
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*/
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SCP_REMAP_CFG3 =
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(uint32_t)addr_map[0xd] << 28 |
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(uint32_t)addr_map[0xf] << 16 |
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(uint32_t)addr_map[0xe] << 8 |
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(uint32_t)addr_map[0xc];
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/* Initialize cache remapping. */
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scp_cache_init();
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}
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int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
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{
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int i;
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uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT;
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for (i = 0; i < ARRAY_SIZE(addr_map); i++) {
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if (addr_map[i] != msb)
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continue;
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*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
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(i << SCP_REMAP_ADDR_SHIFT);
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return EC_SUCCESS;
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}
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return EC_ERROR_INVAL;
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}
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int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
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{
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int i = scp_addr >> SCP_REMAP_ADDR_SHIFT;
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if (addr_map[i] == MAP_INVALID)
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return EC_ERROR_INVAL;
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*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
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(addr_map[i] << SCP_REMAP_ADDR_SHIFT);
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return EC_SUCCESS;
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}
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#ifdef CONFIG_DRAM_BASE
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BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
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BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
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#endif
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int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr)
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{
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uintptr_t lsb;
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if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR)
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return EC_ERROR_INVAL;
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lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
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if (lsb > CACHE_TRANS_AP_SIZE)
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return EC_ERROR_INVAL;
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*scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb;
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return EC_SUCCESS;
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}
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int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
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{
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uintptr_t lsb;
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if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
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CACHE_TRANS_SCP_CACHE_ADDR)
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return EC_ERROR_INVAL;
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lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
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if (lsb >= CACHE_TRANS_AP_SIZE)
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return EC_ERROR_INVAL;
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*ap_addr = CACHE_TRANS_AP_ADDR | lsb;
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return EC_SUCCESS;
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}
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