498 lines
12 KiB
C
498 lines
12 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "clock.h"
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#include "clock_chip.h"
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "gpio.h"
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#include "gpio_chip.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "hwtimer_chip.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "uartn.h"
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#include "util.h"
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#include "watchdog.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#define WAKE_INTERVAL 61 /* Unit: 61 usec */
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#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */
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/* Low power idle statistics */
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#ifdef CONFIG_LOW_POWER_IDLE
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static int idle_sleep_cnt;
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static int idle_dsleep_cnt;
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static uint64_t idle_dsleep_time_us;
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/*
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* Fixed amount of time to keep the console in use flag true after boot in
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* order to give a permanent window in which the low speed clock is not used.
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*/
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#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
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static int console_in_use_timeout_sec = 15;
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static timestamp_t console_expire_time;
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#endif
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/**
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* Enable clock to peripheral by setting the CGC register pertaining
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* to run, sleep, and/or deep sleep modes.
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*
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* @param offset Offset of the peripheral. See enum clock_gate_offsets.
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* @param mask Bit mask of the bits within CGC reg to set.
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* @param mode no used
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*/
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void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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/* Don't support for different mode */
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uint8_t reg_mask = mask & 0xff;
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/* Set PD bit to 0 */
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NPCX_PWDWN_CTL(offset) &= ~reg_mask;
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/* Wait for clock change to take affect. */
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clock_wait_cycles(3);
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}
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/**
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* Disable clock to peripheral by setting the CGC register pertaining
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* to run, sleep, and/or deep sleep modes.
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*
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* @param offset Offset of the peripheral. See enum clock_gate_offsets.
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* @param mask Bit mask of the bits within CGC reg to clear.
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* @param mode no used
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*/
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void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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/* Don't support for different mode */
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uint8_t reg_mask = mask & 0xff;
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/* Set PD bit to 1 */
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NPCX_PWDWN_CTL(offset) |= reg_mask;
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}
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/*****************************************************************************/
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/* IC specific low-level driver */
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/**
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* Set the CPU clocks and PLLs.
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*/
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void clock_init(void)
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{
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#if defined(CONFIG_CLOCK_SRC_EXTERNAL) && defined(NPCX_EXT32K_OSC_SUPPORT)
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/* Select external 32kHz crystal oscillator as LFCLK source. */
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SET_BIT(NPCX_LFCGCTL2, NPCX_LFCGCTL2_XT_OSC_SL_EN);
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#endif
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/*
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* Configure frequency multiplier M/N values according to
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* the requested OSC_CLK (Unit:Hz).
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*/
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NPCX_HFCGN = HFCGN;
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NPCX_HFCGML = HFCGML;
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NPCX_HFCGMH = HFCGMH;
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/* Load M and N values into the frequency multiplier */
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SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
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/* Wait for stable */
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while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
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;
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/* Set all clock prescalers of core and peripherals. */
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#if defined(CHIP_FAMILY_NPCX5)
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NPCX_HFCGP = (FPRED << 4);
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NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
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#elif defined(CHIP_FAMILY_NPCX7)
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NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
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NPCX_HFCBCD = (FIUDIV << 4);
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NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
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NPCX_HFCBCD2 = APB3DIV;
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#endif
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/* Notify modules of frequency change */
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hook_notify(HOOK_FREQ_CHANGE);
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/* Configure alt. clock GPIOs (eg. optional 32KHz clock) */
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gpio_config_module(MODULE_CLOCK, 1);
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}
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#if defined(CHIP_FAMILY_NPCX5)
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void clock_turbo(void)
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{
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/* Configure Frequency multiplier values to 50MHz */
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NPCX_HFCGN = 0x02;
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NPCX_HFCGML = 0xEC;
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NPCX_HFCGMH = 0x0B;
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/* Load M and N values into the frequency multiplier */
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SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
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/* Wait for stable */
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while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
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;
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/* Keep Core CLK & FMCLK are the same if Core CLK exceed 33MHz */
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NPCX_HFCGP = 0x00;
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/*
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* Let APB2 equals Core CLK/2 if default APB2 clock is divisible
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* by 1MHz
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*/
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NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
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}
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#elif defined(CHIP_FAMILY_NPCX7)
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void clock_turbo(void)
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{
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/*
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* Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
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* CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
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*/
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NPCX_HFCGP = 0x01;
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NPCX_HFCBCD = BIT(4);
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}
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void clock_normal(void)
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{
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/* Set CORE_CLK (CPU), AHB6_CLK and FIU_CLK back to original values. */
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NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
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NPCX_HFCBCD = (FIUDIV << 4);
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}
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void clock_enable_module(enum module_id module, int enable)
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{
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/* Assume we have a single task using MODULE_FAST_CPU */
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if (module == MODULE_FAST_CPU) {
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if (enable)
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clock_turbo();
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else
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clock_normal();
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}
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}
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#endif
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/**
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* Return the current clock frequency in Hz.
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*/
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int clock_get_freq(void)
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{
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return CORE_CLK;
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}
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/**
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* Return the current FMUL clock frequency in Hz.
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*/
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int clock_get_fm_freq(void)
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{
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return FMCLK;
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}
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/**
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* Return the current APB1 clock frequency in Hz.
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*/
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int clock_get_apb1_freq(void)
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{
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return NPCX_APB_CLOCK(1);
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}
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/**
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* Return the current APB2 clock frequency in Hz.
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*/
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int clock_get_apb2_freq(void)
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{
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return NPCX_APB_CLOCK(2);
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}
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/**
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* Return the current APB3 clock frequency in Hz.
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*/
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#if defined(CHIP_FAMILY_NPCX7)
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int clock_get_apb3_freq(void)
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{
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return NPCX_APB_CLOCK(3);
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}
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#endif
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/**
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* Wait for a number of clock cycles.
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*
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* Simple busy waiting for use before clocks/timers are initialized.
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*
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* @param cycles Number of cycles to wait.
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*/
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void clock_wait_cycles(uint32_t cycles)
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{
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asm volatile("1: subs %0, #1\n"
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" bne 1b\n" : "+r"(cycles));
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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void clock_refresh_console_in_use(void)
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{
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/* Set console in use expire time. */
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console_expire_time = get_time();
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console_expire_time.val += console_in_use_timeout_sec * SECOND;
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return;
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}
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#if defined(CHIP_FAMILY_NPCX5)
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void clock_uart2gpio(void)
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{
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/* Is pimux to UART? */
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if (npcx_is_uart()) {
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/* Flush tx before enter deep idle */
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uart_tx_flush();
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/* Change pinmux to GPIO and disable UART IRQ */
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task_disable_irq(NPCX_IRQ_UART);
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/* Set to GPIO */
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npcx_uart2gpio();
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/* Clear pending wakeup */
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uart_clear_pending_wakeup();
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/* Enable MIWU for GPIO (UARTRX) */
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uart_enable_wakeup(1);
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}
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}
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void clock_gpio2uart(void)
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{
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/* Is Pending bit of GPIO (UARTRX) */
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if (uart_is_wakeup_from_gpio()) {
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/* Refresh console in-use timer */
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clock_refresh_console_in_use();
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/* Disable MIWU for GPIO (UARTRX) */
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uart_enable_wakeup(0);
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/* Go back CR_SIN */
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npcx_gpio2uart();
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/* Enable uart again */
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task_enable_irq(NPCX_IRQ_UART);
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}
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}
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#endif
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/* Idle task. Executed when no tasks are ready to be scheduled. */
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void __idle(void)
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{
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timestamp_t t0, t1;
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uint32_t next_evt;
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uint32_t next_evt_us;
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uint16_t evt_count;
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/*
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* Initialize console in use to true and specify the console expire
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* time in order to give a fixed window on boot in which the low speed
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* clock will not be used in idle.
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*/
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console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
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while (1) {
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/*
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* Disable interrupts before going to deep sleep in order to
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* calculate the appropriate time to wake up. Note: the wfi
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* instruction waits until an interrupt is pending, so it
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* will still wake up even with interrupts disabled.
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*/
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interrupt_disable();
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/* Compute event delay */
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t0 = get_time();
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next_evt = __hw_clock_event_get();
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/* Do we have enough time before next event to deep sleep. */
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if (DEEP_SLEEP_ALLOWED &&
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/*
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* Our HW timer doesn't tick in deep sleep - we do manual
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* adjustment based on sleep duration after wake. Avoid
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* the tricky overflow case by waiting out the period just
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* before overflow.
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*/
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next_evt != EVT_MAX_EXPIRED_US &&
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/* Ensure event hasn't already expired */
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next_evt > t0.le.lo &&
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/* Ensure we have sufficient time before expiration */
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next_evt - t0.le.lo > WAKE_INTERVAL &&
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/* Make sure it's over console expired time */
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t0.val > console_expire_time.val) {
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#if DEBUG_CLK
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/* Use GPIO to indicate SLEEP mode */
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CLEAR_BIT(NPCX_PDOUT(0), 0);
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#endif
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idle_dsleep_cnt++;
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/* Enable Host access wakeup */
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SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
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#if defined(CHIP_FAMILY_NPCX5)
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/* UART-rx(console) become to GPIO (NONE INT mode) */
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clock_uart2gpio();
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#elif defined(CHIP_FAMILY_NPCX7)
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uartn_wui_en(CONFIG_CONSOLE_UART);
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#endif
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/*
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* Disable input buffer of all 1.8v i2c ports before
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* entering deep sleep for better power consumption.
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*/
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gpio_enable_1p8v_i2c_wake_up_input(0);
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/* Set deep idle - instant wake-up mode */
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NPCX_PMCSR = IDLE_PARAMS;
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/* Get current counter value of event timer */
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evt_count = __hw_clock_event_count();
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/*
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* TODO (ML): We found the same symptom of idle occurs
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* after wake-up from deep idle. Please see task.c for
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* more detail.
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* Workaround: Apply the same bypass of idle.
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*/
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asm ("push {r0-r5}\n"
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"wfi\n"
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"ldm %0, {r0-r5}\n"
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"pop {r0-r5}\n"
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"isb\n" :: "r" (0x100A8000)
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);
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/* Get time delay cause of deep idle */
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next_evt_us = __hw_clock_get_sleep_time(evt_count);
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/*
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* Clear PMCSR manually in case there's wake-up between
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* setting it and wfi.
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*/
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|
NPCX_PMCSR = 0;
|
||
|
|
#if defined(CHIP_FAMILY_NPCX5)
|
||
|
|
/* GPIO back to UART-rx (console) */
|
||
|
|
clock_gpio2uart();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Enable input buffer of all 1.8v i2c ports. */
|
||
|
|
gpio_enable_1p8v_i2c_wake_up_input(1);
|
||
|
|
|
||
|
|
/* Record time spent in deep sleep. */
|
||
|
|
idle_dsleep_time_us += next_evt_us;
|
||
|
|
|
||
|
|
/* Fast forward timer according to wake-up timer. */
|
||
|
|
t1.val = t0.val + next_evt_us;
|
||
|
|
/* Leave overflow situation for ITIM32 */
|
||
|
|
if (t1.le.hi == t0.le.hi)
|
||
|
|
force_time(t1);
|
||
|
|
} else {
|
||
|
|
#if DEBUG_CLK
|
||
|
|
/* Use GPIO to indicate NORMAL mode */
|
||
|
|
SET_BIT(NPCX_PDOUT(0), 0);
|
||
|
|
#endif
|
||
|
|
idle_sleep_cnt++;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Using host access to make sure M4 core clock will
|
||
|
|
* return when the eSPI accesses the Host modules if
|
||
|
|
* CSAE bit is set. Please notice this symptom only
|
||
|
|
* occurs at npcx5.
|
||
|
|
*/
|
||
|
|
#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
|
||
|
|
/* Enable Host access wakeup */
|
||
|
|
SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
|
||
|
|
#endif
|
||
|
|
/*
|
||
|
|
* Normal idle : wait for interrupt
|
||
|
|
* TODO (ML): Workaround method for wfi issue.
|
||
|
|
* Please see task.c for more detail
|
||
|
|
*/
|
||
|
|
asm ("push {r0-r5}\n"
|
||
|
|
"wfi\n"
|
||
|
|
"ldm %0, {r0-r5}\n"
|
||
|
|
"pop {r0-r5}\n"
|
||
|
|
"isb\n" :: "r" (0x100A8000)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Restore interrupt
|
||
|
|
* RTOS will leave idle task to handle ISR which wakes up EC
|
||
|
|
*/
|
||
|
|
interrupt_enable();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef CONFIG_LOW_POWER_IDLE
|
||
|
|
/**
|
||
|
|
* Print low power idle statistics
|
||
|
|
*/
|
||
|
|
static int command_idle_stats(int argc, char **argv)
|
||
|
|
{
|
||
|
|
timestamp_t ts = get_time();
|
||
|
|
|
||
|
|
ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt);
|
||
|
|
ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt);
|
||
|
|
ccprintf("Time spent in deep-sleep: %.6lds\n",
|
||
|
|
idle_dsleep_time_us);
|
||
|
|
ccprintf("Total time on: %.6lds\n", ts.val);
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
|
||
|
|
"",
|
||
|
|
"Print last idle stats");
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Configure deep sleep clock settings.
|
||
|
|
*/
|
||
|
|
static int command_dsleep(int argc, char **argv)
|
||
|
|
{
|
||
|
|
int v;
|
||
|
|
|
||
|
|
if (argc > 1) {
|
||
|
|
if (parse_bool(argv[1], &v)) {
|
||
|
|
/*
|
||
|
|
* Force deep sleep not to use low speed clock or
|
||
|
|
* allow it to use the low speed clock.
|
||
|
|
*/
|
||
|
|
if (v)
|
||
|
|
disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
||
|
|
else
|
||
|
|
enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
||
|
|
} else {
|
||
|
|
/* Set console in use timeout. */
|
||
|
|
char *e;
|
||
|
|
v = strtoi(argv[1], &e, 10);
|
||
|
|
if (*e)
|
||
|
|
return EC_ERROR_PARAM1;
|
||
|
|
|
||
|
|
console_in_use_timeout_sec = v;
|
||
|
|
|
||
|
|
/* Refresh console in use to use new timeout. */
|
||
|
|
clock_refresh_console_in_use();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
ccprintf("Sleep mask: %08x\n", sleep_mask);
|
||
|
|
ccprintf("Console in use timeout: %d sec\n",
|
||
|
|
console_in_use_timeout_sec);
|
||
|
|
ccprintf("PMCSR register: 0x%02x\n", NPCX_PMCSR);
|
||
|
|
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
|
||
|
|
"[ on | off | <timeout> sec]",
|
||
|
|
"Deep sleep clock settings:\nUse 'on' to force deep "
|
||
|
|
"sleep not to use low speed clock.\nUse 'off' to "
|
||
|
|
"allow deep sleep to auto-select using the low speed "
|
||
|
|
"clock.\n"
|
||
|
|
"Give a timeout value for the console in use timeout.\n"
|
||
|
|
"See also 'sleepmask'.");
|
||
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|