268 lines
6.9 KiB
C
268 lines
6.9 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI module for Chrome EC */
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "clock.h"
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#include "clock_chip.h"
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#include "registers.h"
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#include "spi.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Console output macros */
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#if !DEBUG_SPI
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#define CPUTS(...)
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#define CPRINTS(...)
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#else
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#define CPUTS(outstr) cputs(CC_SPI, outstr)
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#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
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#endif
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/* SPI IP as SPI master */
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#define SPI_CLK 8000000
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/**
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* Clear SPI data buffer.
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*
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* @param none
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* @return none.
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*/
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static void clear_databuf(void)
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{
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volatile uint8_t dummy __attribute__((unused));
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while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
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dummy = NPCX_SPI_DATA;
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}
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/**
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* Preset SPI operation clock.
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*
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* @param none
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* @return none
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* @notes changed when initial or HOOK_FREQ_CHANGE command
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*/
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void spi_freq_changed(void)
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{
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uint8_t prescaler_divider = 0;
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/* Set clock prescaler divider to SPI module*/
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prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq()
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/ 2 / SPI_CLK);
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if (prescaler_divider >= 1)
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prescaler_divider = prescaler_divider - 1;
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if (prescaler_divider > 0x7F)
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prescaler_divider = 0x7F;
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/* Set core clock division factor in order to obtain the SPI clock */
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NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV)))
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|(prescaler_divider<<NPCX_SPI_CTL1_SCDV);
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST);
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/**
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* Set SPI enabled.
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*
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* @spi_port port to act on. Only one port supported, one gpio.
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* @param enable enabled flag
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* @return success
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*/
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int spi_enable(int port, int enable)
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{
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int i;
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enum gpio_signal gpio;
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if (enable) {
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/* Enabling spi module for gpio configuration */
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gpio_config_module(MODULE_SPI, 1);
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/* GPIO No SPI Select */
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CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
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for (i = 0; i < spi_devices_used; i++) {
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if (spi_devices[i].port != port)
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continue;
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gpio = spi_devices[i].gpio_cs;
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/* Make sure CS# is a GPIO output mode. */
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gpio_set_flags(gpio, GPIO_OUTPUT);
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/* Make sure CS# is deselected */
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gpio_set_level(gpio, 1);
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}
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/* Enabling spi module */
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SET_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
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} else {
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/* Disabling spi module */
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
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for (i = 0; i < spi_devices_used; i++) {
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if (spi_devices[i].port != port)
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continue;
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gpio = spi_devices[i].gpio_cs;
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/* Make sure CS# is deselected */
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gpio_set_level(gpio, 1);
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gpio_set_flags(gpio, GPIO_ODR_HIGH);
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}
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/* Disabling spi module for gpio configuration */
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gpio_config_module(MODULE_SPI, 0);
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/* GPIO No SPI Select */
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SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
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}
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return EC_SUCCESS;
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}
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/**
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* Flush an SPI transaction and receive data from slave.
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*
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* @param spi_device device to talk to
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* @param txdata transfer data
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* @param txlen transfer length
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* @param rxdata receive data
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* @param rxlen receive length
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* @return success
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* @notes set master transaction mode in npcx chip
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*/
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int spi_transaction(const struct spi_device_t *spi_device,
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const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen)
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{
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int i = 0;
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enum gpio_signal gpio = spi_device->gpio_cs;
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static struct mutex spi_lock;
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mutex_lock(&spi_lock);
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/* Make sure CS# is a GPIO output mode. */
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gpio_set_flags(gpio, GPIO_OUTPUT);
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/* Make sure CS# is deselected */
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gpio_set_level(gpio, 1);
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/* Cleaning junk data in the buffer */
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clear_databuf();
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/* Assert CS# to start transaction */
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gpio_set_level(gpio, 0);
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CPRINTS("NPCX_SPI_DATA=%x", NPCX_SPI_DATA);
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CPRINTS("NPCX_SPI_CTL1=%x", NPCX_SPI_CTL1);
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CPRINTS("NPCX_SPI_STAT=%x", NPCX_SPI_STAT);
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/* Writing the data */
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for (i = 0; i < txlen; ++i) {
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/* Making sure we can write */
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while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
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;
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/* Write the data */
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NPCX_SPI_DATA = txdata[i];
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CPRINTS("txdata[i]=%x", txdata[i]);
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/* Waiting till reading is finished */
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while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
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;
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/* Reading the (dummy) data */
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clear_databuf();
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}
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CPRINTS("write end");
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/* Reading the data */
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for (i = 0; i < rxlen; ++i) {
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/* Making sure we can write */
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while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
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;
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/* Write the (dummy) data */
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NPCX_SPI_DATA = 0;
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/* Wait till reading is finished */
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while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
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;
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/* Reading the data */
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rxdata[i] = (uint8_t)NPCX_SPI_DATA;
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CPRINTS("rxdata[i]=%x", rxdata[i]);
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}
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/* Deassert CS# (high) to end transaction */
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gpio_set_level(gpio, 1);
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mutex_unlock(&spi_lock);
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return EC_SUCCESS;
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}
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/**
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* SPI initial.
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*
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* @param none
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* @return none
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*/
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static void spi_init(void)
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{
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int i;
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/* Enable clock for SPI peripheral */
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clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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/* Disabling spi module */
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for (i = 0; i < spi_devices_used; i++)
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spi_enable(spi_devices[i].port, 0);
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/* Disabling spi irq */
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIR);
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIW);
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/* Setting clocking mode to normal mode */
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCM);
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/* Setting 8bit mode transfer */
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_MOD);
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/* Set core clock division factor in order to obtain the spi clock */
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spi_freq_changed();
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/* We emit zeros in idle (default behaivor) */
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CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);
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CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
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CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
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NPCX_DEV_CTL4_SPI_SP_SEL));
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/* Cleaning junk data in the buffer */
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clear_databuf();
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}
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DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
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/*****************************************************************************/
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/* Console commands */
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#ifdef CONFIG_CMD_SPI_FLASH
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static int printrx(const char *desc, const uint8_t *txdata, int txlen,
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int rxlen)
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{
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uint8_t rxdata[32];
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int rv;
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int i;
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rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
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if (rv)
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return rv;
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CPRINTS("%-12s:", desc);
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for (i = 0; i < rxlen; i++)
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CPRINTS(" 0x%02x", rxdata[i]);
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CPUTS("\n");
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return EC_SUCCESS;
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}
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static int command_spirom(int argc, char **argv)
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{
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uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
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uint8_t txjedec[] = {0x9f};
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uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
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uint8_t txsr1[] = {0x05};
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uint8_t txsr2[] = {0x35};
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spi_enable(CONFIG_SPI_FLASH_PORT, 1);
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printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
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printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
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printrx("Unique ID", txunique, sizeof(txunique), 8);
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printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
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printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
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spi_enable(CONFIG_SPI_FLASH_PORT, 0);
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
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NULL,
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"Test reading SPI EEPROM");
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#endif
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