447 lines
11 KiB
C
447 lines
11 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "chipset.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
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/* High-speed oscillator default is 64 MHz */
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#define STM32_HSI_CLOCK 64000000
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/* Low-speed oscillator is 32-Khz */
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#define STM32_LSI_CLOCK 32000
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/*
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* LPTIM is a 16-bit counter clocked by LSI
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* with /4 prescaler (2^2): period 125 us, full range ~8s
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*/
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#define LPTIM_PRESCALER_LOG2 2
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#define LPTIM_PRESCALER BIT(LPTIM_PRESCALER_LOG2)
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#define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER))
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/*
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* PLL1 configuration:
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* CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
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* = 64 / 4 * 50 / 2
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* = 400 Mhz
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* System clock = 400 Mhz
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* HPRE = /2 => AHB/Timer clock = 200 Mhz
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*/
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#if !defined(PLL1_DIVM) && !defined(PLL1_DIVN) && !defined(PLL1_DIVP)
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#define PLL1_DIVM 4
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#define PLL1_DIVN 50
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#define PLL1_DIVP 2
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#endif
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#define PLL1_FREQ (STM32_HSI_CLOCK / PLL1_DIVM * PLL1_DIVN / PLL1_DIVP)
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/* Flash latency settings for AHB/ACLK at 64 Mhz and Vcore in VOS1 range */
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#define FLASH_ACLK_64MHZ (STM32_FLASH_ACR_WRHIGHFREQ_85MHZ | \
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(0 << STM32_FLASH_ACR_LATENCY_SHIFT))
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/* Flash latency settings for AHB/ACLK at 200 Mhz and Vcore in VOS1 range */
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#define FLASH_ACLK_200MHZ (STM32_FLASH_ACR_WRHIGHFREQ_285MHZ | \
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(2 << STM32_FLASH_ACR_LATENCY_SHIFT))
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enum clock_osc {
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OSC_HSI = 0, /* High-speed internal oscillator */
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OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */
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OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */
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OSC_PLL, /* PLL */
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};
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static int freq = STM32_HSI_CLOCK;
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static int current_osc = OSC_HSI;
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int clock_get_freq(void)
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{
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return freq;
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}
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int clock_get_timer_freq(void)
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{
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return clock_get_freq();
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}
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void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
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{
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volatile uint32_t dummy __attribute__((unused));
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if (bus == BUS_AHB) {
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while (cycles--)
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dummy = STM32_GPIO_IDR(GPIO_A);
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} else { /* APB */
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while (cycles--)
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dummy = STM32_USART_BRR(STM32_USART1_BASE);
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}
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}
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static void clock_flash_latency(uint32_t target_acr)
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{
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STM32_FLASH_ACR(0) = target_acr;
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while (STM32_FLASH_ACR(0) != target_acr)
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;
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}
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static void clock_enable_osc(enum clock_osc osc)
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{
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uint32_t ready;
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uint32_t on;
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switch (osc) {
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case OSC_HSI:
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ready = STM32_RCC_CR_HSIRDY;
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on = STM32_RCC_CR_HSION;
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break;
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case OSC_PLL:
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ready = STM32_RCC_CR_PLL1RDY;
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on = STM32_RCC_CR_PLL1ON;
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break;
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default:
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return;
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}
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if (!(STM32_RCC_CR & ready)) {
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STM32_RCC_CR |= on;
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while (!(STM32_RCC_CR & ready))
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;
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}
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}
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static void clock_switch_osc(enum clock_osc osc)
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{
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uint32_t sw;
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uint32_t sws;
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switch (osc) {
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case OSC_HSI:
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sw = STM32_RCC_CFGR_SW_HSI;
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sws = STM32_RCC_CFGR_SWS_HSI;
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break;
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case OSC_PLL:
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sw = STM32_RCC_CFGR_SW_PLL1;
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sws = STM32_RCC_CFGR_SWS_PLL1;
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break;
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default:
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return;
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}
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STM32_RCC_CFGR = sw;
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while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
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;
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}
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static void switch_voltage_scale(uint32_t vos)
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{
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STM32_PWR_D3CR &= ~STM32_PWR_D3CR_VOSMASK;
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STM32_PWR_D3CR |= vos;
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while (!(STM32_PWR_D3CR & STM32_PWR_D3CR_VOSRDY))
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;
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}
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static void clock_set_osc(enum clock_osc osc)
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{
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if (osc == current_osc)
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return;
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hook_notify(HOOK_PRE_FREQ_CHANGE);
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switch (osc) {
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case OSC_HSI:
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/* Switch to HSI */
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clock_switch_osc(osc);
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freq = STM32_HSI_CLOCK;
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/* Restore /1 HPRE (AHB prescaler) */
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STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1
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| STM32_RCC_D1CFGR_D1PPRE_DIV1
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| STM32_RCC_D1CFGR_D1CPRE_DIV1;
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/* Use more optimized flash latency settings for 64-MHz ACLK */
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clock_flash_latency(FLASH_ACLK_64MHZ);
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/* Turn off the PLL1 to save power */
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STM32_RCC_CR &= ~STM32_RCC_CR_PLL1ON;
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switch_voltage_scale(STM32_PWR_D3CR_VOS3);
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break;
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case OSC_PLL:
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switch_voltage_scale(STM32_PWR_D3CR_VOS1);
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/* Configure PLL1 using 64 Mhz HSI as input */
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STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI |
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STM32_RCC_PLLCKSEL_DIVM1(PLL1_DIVM);
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/* in integer mode, wide range VCO with 16Mhz input, use divP */
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STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE
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| STM32_RCC_PLLCFG_PLL1RGE_8M_16M
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| STM32_RCC_PLLCFG_DIVP1EN;
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STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(PLL1_DIVP)
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| STM32_RCC_PLLDIV_DIVN(PLL1_DIVN);
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/* turn on PLL1 and wait that it's ready */
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clock_enable_osc(OSC_PLL);
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/* Put /2 on HPRE (AHB prescaler) to keep at the 200Mhz max */
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STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2
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| STM32_RCC_D1CFGR_D1PPRE_DIV1
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| STM32_RCC_D1CFGR_D1CPRE_DIV1;
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freq = PLL1_FREQ / 2;
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/* Increase flash latency before transition the clock */
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clock_flash_latency(FLASH_ACLK_200MHZ);
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/* Switch to PLL */
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clock_switch_osc(OSC_PLL);
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break;
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default:
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break;
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}
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current_osc = osc;
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hook_notify(HOOK_FREQ_CHANGE);
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}
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void clock_enable_module(enum module_id module, int enable)
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{
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/* Assume we have a single task using MODULE_FAST_CPU */
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if (module == MODULE_FAST_CPU) {
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/* the PLL would be off in low power mode, disable it */
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if (enable)
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disable_sleep(SLEEP_MASK_PLL);
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else
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enable_sleep(SLEEP_MASK_PLL);
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clock_set_osc(enable ? OSC_PLL : OSC_HSI);
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}
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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/* Low power idle statistics */
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static int idle_sleep_cnt;
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static int idle_dsleep_cnt;
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static uint64_t idle_dsleep_time_us;
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static int dsleep_recovery_margin_us = 1000000;
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/* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */
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#define STOP_MODE_LATENCY 50 /* us */
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static void low_power_init(void)
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{
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/* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */
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STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R &
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~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK)
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| STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
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/* configure LPTIM1 as our 1-Khz low power timer in STOP mode */
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STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1;
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STM32_LPTIM_CR(1) = 0; /* ensure it's disabled before configuring */
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STM32_LPTIM_CFGR(1) = LPTIM_PRESCALER_LOG2 << 9; /* Prescaler /4 */
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STM32_LPTIM_IER(1) = STM32_LPTIM_INT_CMPM; /* Compare int for wake-up */
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/* Start the 16-bit free-running counter */
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STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE;
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STM32_LPTIM_ARR(1) = 0xFFFF;
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STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE | STM32_LPTIM_CR_CNTSTRT;
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task_enable_irq(STM32_IRQ_LPTIM1);
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/* Wake-up interrupts from EXTI for USART and LPTIM */
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STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */
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STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
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/* optimize power vs latency in STOP mode */
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STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
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| STM32_PWR_CR_SVOS5
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| STM32_PWR_CR_FLPS;
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}
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void clock_refresh_console_in_use(void)
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{
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}
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void lptim_interrupt(void)
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{
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STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
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}
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DECLARE_IRQ(STM32_IRQ_LPTIM1, lptim_interrupt, 2);
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static uint16_t lptim_read(void)
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{
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uint16_t cnt;
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do {
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cnt = STM32_LPTIM_CNT(1);
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} while (cnt != STM32_LPTIM_CNT(1));
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return cnt;
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}
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static void set_lptim_event(int delay_us, uint16_t *lptim_cnt)
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{
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uint16_t cnt = lptim_read();
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STM32_LPTIM_CMP(1) = cnt + MIN(delay_us / LPTIM_PERIOD_US - 1, 0xffff);
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/* clean-up previous event */
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STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
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*lptim_cnt = cnt;
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}
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void __idle(void)
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{
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timestamp_t t0;
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int next_delay;
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int margin_us, t_diff;
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uint16_t lptim0;
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while (1) {
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asm volatile("cpsid i");
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t0 = get_time();
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next_delay = __hw_clock_event_get() - t0.le.lo;
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if (DEEP_SLEEP_ALLOWED &&
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next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) {
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/* deep-sleep in STOP mode */
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idle_dsleep_cnt++;
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uart_enable_wakeup(1);
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/* set deep sleep bit */
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CPU_SCB_SYSCTRL |= 0x4;
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set_lptim_event(next_delay - STOP_MODE_LATENCY,
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&lptim0);
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/* ensure outstanding memory transactions complete */
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asm volatile("dsb");
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asm("wfi");
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CPU_SCB_SYSCTRL &= ~0x4;
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/* fast forward timer according to low power counter */
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if (STM32_PWR_CPUCR & STM32_PWR_CPUCR_STOPF) {
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uint16_t lptim_dt = lptim_read() - lptim0;
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t_diff = (int)lptim_dt * LPTIM_PERIOD_US;
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t0.val = t0.val + t_diff;
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force_time(t0);
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/* clear STOPF flag */
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STM32_PWR_CPUCR |= STM32_PWR_CPUCR_CSSF;
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} else { /* STOP entry was aborted, no fixup */
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t_diff = 0;
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}
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uart_enable_wakeup(0);
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/* Record time spent in deep sleep. */
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idle_dsleep_time_us += t_diff;
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/* Calculate how close we were to missing deadline */
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margin_us = next_delay - t_diff;
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if (margin_us < 0)
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/* Use CPUTS to save stack space */
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CPUTS("Overslept!\n");
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/* Record the closest to missing a deadline. */
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if (margin_us < dsleep_recovery_margin_us)
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dsleep_recovery_margin_us = margin_us;
|
||
|
|
} else {
|
||
|
|
idle_sleep_cnt++;
|
||
|
|
|
||
|
|
/* normal idle : only CPU clock stopped */
|
||
|
|
asm("wfi");
|
||
|
|
}
|
||
|
|
asm volatile("cpsie i");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_CMD_IDLE_STATS
|
||
|
|
/**
|
||
|
|
* Print low power idle statistics
|
||
|
|
*/
|
||
|
|
static int command_idle_stats(int argc, char **argv)
|
||
|
|
{
|
||
|
|
timestamp_t ts = get_time();
|
||
|
|
|
||
|
|
ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt);
|
||
|
|
ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt);
|
||
|
|
ccprintf("Time spent in deep-sleep: %.6lds\n",
|
||
|
|
idle_dsleep_time_us);
|
||
|
|
ccprintf("Total time on: %.6lds\n", ts.val);
|
||
|
|
ccprintf("Deep-sleep closest to wake deadline: %dus\n",
|
||
|
|
dsleep_recovery_margin_us);
|
||
|
|
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
|
||
|
|
"",
|
||
|
|
"Print last idle stats");
|
||
|
|
#endif /* CONFIG_CMD_IDLE_STATS */
|
||
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|
||
|
|
|
||
|
|
void clock_init(void)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* STM32H743 Errata 2.2.15:
|
||
|
|
* 'Reading from AXI SRAM might lead to data read corruption'
|
||
|
|
*
|
||
|
|
* limit concurrent read access on AXI master to 1.
|
||
|
|
*/
|
||
|
|
STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Lock (SCUEN=0) power configuration with the LDO enabled.
|
||
|
|
*
|
||
|
|
* The STM32H7 Reference Manual says:
|
||
|
|
* The lower byte of this register is written once after POR and shall
|
||
|
|
* be written before changing VOS level or ck_sys clock frequency.
|
||
|
|
*
|
||
|
|
* The interesting side-effect of this that while the LDO is enabled by
|
||
|
|
* default at startup, if we enter STOP mode without locking it the MCU
|
||
|
|
* seems to freeze forever.
|
||
|
|
*/
|
||
|
|
STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN;
|
||
|
|
/*
|
||
|
|
* Ensure the SPI is always clocked at the same frequency
|
||
|
|
* by putting it on the fixed 64-Mhz HSI clock.
|
||
|
|
* per_ck is clocked directly by the HSI (as per the default settings).
|
||
|
|
*/
|
||
|
|
STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R &
|
||
|
|
~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
|
||
|
|
STM32_RCC_D2CCIP1R_SPI45SEL_MASK))
|
||
|
|
| STM32_RCC_D2CCIP1R_SPI123SEL_PERCK
|
||
|
|
| STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
|
||
|
|
|
||
|
|
/* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */
|
||
|
|
clock_flash_latency(FLASH_ACLK_64MHZ);
|
||
|
|
|
||
|
|
/* Ensure that LSI is ON to clock LPTIM1 and IWDG */
|
||
|
|
STM32_RCC_CSR |= STM32_RCC_CSR_LSION;
|
||
|
|
while (!(STM32_RCC_CSR & STM32_RCC_CSR_LSIRDY))
|
||
|
|
;
|
||
|
|
|
||
|
|
#ifdef CONFIG_LOW_POWER_IDLE
|
||
|
|
low_power_init();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static int command_clock(int argc, char **argv)
|
||
|
|
{
|
||
|
|
if (argc >= 2) {
|
||
|
|
if (!strcasecmp(argv[1], "hsi"))
|
||
|
|
clock_set_osc(OSC_HSI);
|
||
|
|
else if (!strcasecmp(argv[1], "pll"))
|
||
|
|
clock_set_osc(OSC_PLL);
|
||
|
|
else
|
||
|
|
return EC_ERROR_PARAM1;
|
||
|
|
}
|
||
|
|
ccprintf("Clock frequency is now %d Hz\n", freq);
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(clock, command_clock,
|
||
|
|
"hsi | pll", "Set clock frequency");
|