61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Memory mapping */
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#define CONFIG_FLASH_SIZE (2048 * 1024)
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/* 3 regions type: 32K, 128K and 256K */
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#define SIZE_32KB (32 * 1024)
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#define SIZE_128KB (128 * 1024)
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#define SIZE_256KB (256 * 1024)
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#define CONFIG_FLASH_REGION_TYPE_COUNT 3
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#define CONFIG_FLASH_MULTIPLE_REGION \
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(5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB)
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/* Erasing 256K can take up to 2s, need to defer erase. */
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#define CONFIG_FLASH_DEFERRED_ERASE
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/* minimum write size for 3.3V. 1 for 1.8V */
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#define STM32_FLASH_WRITE_SIZE_1800 1
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#define STM32_FLASH_WS_DIV_1800 16000000
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#define STM32_FLASH_WRITE_SIZE_3300 4
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#define STM32_FLASH_WS_DIV_3300 30000000
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/* No page mode on STM32F, so no benefit to larger write sizes */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
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/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
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/* SRAM1: 368kB 0x20020000 - 0x2007BFFF */
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/* SRAM2: 16kB 0x2007C000 - 0x2007FFFF */
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE 0x00080000
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_SIZE (1024 * 1024)
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#define CONFIG_RW_MEM_OFF (1024 * 1024)
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#define CONFIG_RW_SIZE (1024 * 1024)
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#define CONFIG_RO_STORAGE_OFF 0
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#define CONFIG_RW_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
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#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
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(CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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#undef I2C_PORT_COUNT
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#define I2C_PORT_COUNT 4
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/* Use PSTATE embedded in the RO image, not in its own erase block */
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#define CONFIG_FLASH_PSTATE
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#undef CONFIG_FLASH_PSTATE_BANK
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 109
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