335 lines
8.7 KiB
C
335 lines
8.7 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "console.h"
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#include "dma.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_DMA, outstr)
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#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
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#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
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stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS };
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/* Callback data to use when IRQ fires */
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static struct {
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void (*cb)(void *); /* Callback function to call */
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void *cb_data; /* Callback data for callback function */
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} dma_irq[STM32_DMAS_TOTAL_COUNT];
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/**
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* Return the IRQ for the DMA stream
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*
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* @param stream stream number
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* @return IRQ for the stream
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*/
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static int dma_get_irq(enum dma_channel stream)
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{
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if (stream < STM32_DMA1_STREAM6)
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return STM32_IRQ_DMA1_STREAM0 + stream;
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if (stream == STM32_DMA1_STREAM7)
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return STM32_IRQ_DMA1_STREAM7;
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if (stream < STM32_DMA2_STREAM5)
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return STM32_IRQ_DMA2_STREAM0 + stream - STM32_DMA2_STREAM0;
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else
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return STM32_IRQ_DMA2_STREAM5 + stream - STM32_DMA2_STREAM5;
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}
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stm32_dma_regs_t *dma_get_ctrl(enum dma_channel stream)
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{
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return STM32_DMA_REGS[stream / STM32_DMAS_COUNT];
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}
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stm32_dma_stream_t *dma_get_channel(enum dma_channel stream)
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{
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stm32_dma_regs_t *dma = dma_get_ctrl(stream);
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return &dma->stream[stream % STM32_DMAS_COUNT];
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}
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#ifdef CHIP_FAMILY_STM32H7
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void dma_select_channel(enum dma_channel channel, uint8_t req)
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{
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STM2_DMAMUX_CxCR(DMAMUX1, channel) = req;
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}
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#endif
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void dma_disable(enum dma_channel ch)
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{
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stm32_dma_stream_t *stream = dma_get_channel(ch);
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if (stream->scr & STM32_DMA_CCR_EN) {
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stream->scr &= ~STM32_DMA_CCR_EN;
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while (stream->scr & STM32_DMA_CCR_EN)
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;
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}
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}
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void dma_disable_all(void)
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{
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int ch;
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for (ch = 0; ch < STM32_DMAS_TOTAL_COUNT; ch++)
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dma_disable(ch);
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}
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/**
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* Prepare a stream for use and start it
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*
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* @param stream stream to read
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* @param count Number of bytes to transfer
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* @param periph Pointer to peripheral data register
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* @param memory Pointer to memory address for receive/transmit
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* @param flags DMA flags for the control register.
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*/
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static void prepare_stream(enum dma_channel stream, unsigned count,
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void *periph, void *memory, unsigned flags)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
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dma_disable(stream);
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dma_clear_isr(stream);
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/* Following the order in DocID026448 Rev 1 (RM0383) p181 */
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dma_stream->spar = (uint32_t)periph;
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dma_stream->sm0ar = (uint32_t)memory;
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dma_stream->sndtr = count;
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dma_stream->scr = ccr;
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ccr |= flags & STM32_DMA_CCR_CHANNEL_MASK;
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dma_stream->scr = ccr;
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dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
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ccr |= flags;
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dma_stream->scr = ccr;
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}
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void dma_go(stm32_dma_stream_t *stream)
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{
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/* Flush data in write buffer so that DMA can get the latest data */
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asm volatile("dsb;");
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/* Fire it up */
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stream->scr |= STM32_DMA_CCR_EN;
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}
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void dma_prepare_tx(const struct dma_option *option, unsigned count,
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const void *memory)
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{
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/*
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* Cast away const for memory pointer; this is ok because we know
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* we're preparing the stream for transmit.
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*/
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prepare_stream(option->channel, count, option->periph, (void *)memory,
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STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
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option->flags);
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}
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void dma_start_rx(const struct dma_option *option, unsigned count,
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void *memory)
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{
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stm32_dma_stream_t *stream = dma_get_channel(option->channel);
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prepare_stream(option->channel, count, option->periph, memory,
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STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
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option->flags);
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dma_go(stream);
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}
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int dma_bytes_done(stm32_dma_stream_t *stream, int orig_count)
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{
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/*
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* Note that we're intentionally not checking that DMA is enabled here
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* because there is a race when the hardware stops the transfer:
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*
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* From Section 9.3.14 DMA transfer completion in RM0402 Rev 5
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* https://www.st.com/resource/en/reference_manual/dm00180369.pdf:
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* If the stream is configured in non-circular mode, after the end of
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* the transfer (that is when the number of data to be transferred
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* reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is
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* cleared by Hardware) and no DMA request is served unless the software
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* reprograms the stream and re-enables it (by setting the EN bit in the
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* DMA_SxCR register).
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*
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* See http://b/132444384 for full details.
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*/
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return orig_count - stream->sndtr;
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}
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bool dma_is_enabled(stm32_dma_stream_t *stream)
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{
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return (stream->scr & STM32_DMA_CCR_EN);
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}
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#ifdef CONFIG_DMA_HELP
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void dma_dump(enum dma_channel stream)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n",
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dma_stream->scr, dma_stream->sndtr, dma_stream->spar,
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dma_stream->sm0ar, dma_stream->sfcr);
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CPRINTF("stream %d, isr=%x, ifcr=%x\n",
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stream,
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STM32_DMA_GET_ISR(stream),
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STM32_DMA_GET_IFCR(stream));
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}
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void dma_check(enum dma_channel stream, char *buf)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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int count;
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int i;
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count = dma_stream->sndtr;
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CPRINTF("c=%d\n", count);
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udelay(100 * MSEC);
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CPRINTF("c=%d\n", dma_stream->sndtr);
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for (i = 0; i < count; i++)
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CPRINTF("%02x ", buf[i]);
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udelay(100 * MSEC);
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CPRINTF("c=%d\n", dma_stream->sndtr);
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for (i = 0; i < count; i++)
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CPRINTF("%02x ", buf[i]);
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}
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/* Run a check of memory-to-memory DMA */
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void dma_test(enum dma_channel stream)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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uint32_t ctrl;
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char periph[32], memory[32];
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unsigned count = sizeof(periph);
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int i;
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memset(memory, '\0', sizeof(memory));
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for (i = 0; i < count; i++)
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periph[i] = 10 + i;
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dma_clear_isr(stream);
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/* Following the order in Doc ID 15965 Rev 5 p194 */
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dma_stream->spar = (uint32_t)periph;
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dma_stream->sm0ar = (uint32_t)memory;
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dma_stream->sndtr = count;
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dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
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ctrl = STM32_DMA_CCR_PL_MEDIUM;
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dma_stream->scr = ctrl;
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ctrl |= STM32_DMA_CCR_MINC;
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ctrl |= STM32_DMA_CCR_DIR_M2M;
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ctrl |= STM32_DMA_CCR_PINC;
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dma_stream->scr = ctrl;
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dma_dump(stream);
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dma_stream->scr = ctrl | STM32_DMA_CCR_EN;
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for (i = 0; i < count; i++)
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CPRINTF("%d/%d ", periph[i], memory[i]);
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CPRINTF("\ncount=%d\n", dma_stream->sndtr);
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dma_dump(stream);
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}
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#endif /* CONFIG_DMA_HELP */
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void dma_init(void)
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{
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STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1 | STM32_RCC_HB1_DMA2;
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}
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int dma_wait(enum dma_channel stream)
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{
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timestamp_t deadline;
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deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
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while ((STM32_DMA_GET_ISR(stream) & STM32_DMA_TCIF) == 0) {
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if (deadline.val <= get_time().val)
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return EC_ERROR_TIMEOUT;
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udelay(DMA_POLLING_INTERVAL_US);
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}
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return EC_SUCCESS;
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}
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static inline void _dma_wake_callback(void *cb_data)
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{
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task_id_t id = (task_id_t)(int)cb_data;
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if (id != TASK_ID_INVALID)
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task_set_event(id, TASK_EVENT_DMA_TC, 0);
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}
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void dma_enable_tc_interrupt(enum dma_channel stream)
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{
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dma_enable_tc_interrupt_callback(stream, _dma_wake_callback,
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(void *)(int)task_get_current());
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}
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void dma_enable_tc_interrupt_callback(enum dma_channel stream,
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void (*callback)(void *),
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void *callback_data)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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dma_irq[stream].cb = callback;
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dma_irq[stream].cb_data = callback_data;
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dma_stream->scr |= STM32_DMA_CCR_TCIE;
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task_enable_irq(dma_get_irq(stream));
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}
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void dma_disable_tc_interrupt(enum dma_channel stream)
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{
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stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
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dma_stream->scr &= ~STM32_DMA_CCR_TCIE;
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task_disable_irq(dma_get_irq(stream));
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dma_irq[stream].cb = NULL;
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dma_irq[stream].cb_data = NULL;
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}
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void dma_clear_isr(enum dma_channel stream)
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{
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STM32_DMA_SET_IFCR(stream, STM32_DMA_ALL);
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}
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#ifdef CONFIG_DMA_DEFAULT_HANDLERS
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#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x)
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#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x)
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#define DECLARE_DMA_IRQ(dma, x) \
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void STM32_DMA_FCT(dma, x)(void) \
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{ \
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dma_clear_isr(STM32_DMA_IDX(dma, x)); \
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if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \
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(*dma_irq[STM32_DMA_IDX(dma, x)].cb) \
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(dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
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} \
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DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \
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STM32_DMA_FCT(dma, x), 1);
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DECLARE_DMA_IRQ(1, 0);
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DECLARE_DMA_IRQ(1, 1);
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DECLARE_DMA_IRQ(1, 2);
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DECLARE_DMA_IRQ(1, 3);
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DECLARE_DMA_IRQ(1, 4);
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DECLARE_DMA_IRQ(1, 5);
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DECLARE_DMA_IRQ(1, 6);
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DECLARE_DMA_IRQ(1, 7);
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DECLARE_DMA_IRQ(2, 0);
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DECLARE_DMA_IRQ(2, 1);
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DECLARE_DMA_IRQ(2, 2);
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DECLARE_DMA_IRQ(2, 3);
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DECLARE_DMA_IRQ(2, 4);
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DECLARE_DMA_IRQ(2, 5);
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DECLARE_DMA_IRQ(2, 6);
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DECLARE_DMA_IRQ(2, 7);
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#endif /* CONFIG_DMA_DEFAULT_HANDLERS */
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