426 lines
10 KiB
C
426 lines
10 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "chipset.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "dma.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "host_command.h"
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#include "i2c.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_I2C, outstr)
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#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
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#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
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/*
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* Transmit timeout in microseconds
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*
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* In theory we shouldn't have a timeout here (at least when we're in slave
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* mode). The slave is supposed to wait forever for the master to read bytes.
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* ...but we're going to keep the timeout to make sure we're robust. It may in
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* fact be needed if the host resets itself mid-read.
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*
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* NOTE: One case where this timeout is useful is when the battery
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* flips out. The battery may flip out and hold lines low for up to
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* 25ms. If we just wait it will eventually let them go.
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*/
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#define I2C_TX_TIMEOUT_MASTER (30 * MSEC)
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/*
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* Delay 5us in bitbang mode. That gives us roughly 5us low and 5us high or
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* a frequency of 100kHz.
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*/
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#define I2C_BITBANG_HALF_CYCLE_US 5
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#ifdef CONFIG_I2C_DEBUG
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static void dump_i2c_reg(int port, const char *what)
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{
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CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s",
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STM32_I2C_CR1(port),
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STM32_I2C_CR2(port),
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STM32_I2C_SR1(port),
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STM32_I2C_SR2(port),
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what);
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}
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#else
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static inline void dump_i2c_reg(int port, const char *what)
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{
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}
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#endif
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/**
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* Wait for SR1 register to contain the specified mask.
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*
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* Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
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* EC_ERROR_UNKNOWN if an error bit appeared in the status register.
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*/
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static int wait_sr1(int port, int mask)
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{
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uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
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while (get_time().val < timeout) {
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int sr1 = STM32_I2C_SR1(port);
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/* Check for errors */
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if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR |
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STM32_I2C_SR1_AF)) {
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dump_i2c_reg(port, "wait_sr1 failed");
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return EC_ERROR_UNKNOWN;
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}
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/* Check for desired mask */
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if ((sr1 & mask) == mask)
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return EC_SUCCESS;
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/* I2C is slow, so let other things run while we wait */
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usleep(100);
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}
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return EC_ERROR_TIMEOUT;
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}
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/**
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* Send a start condition and slave address on the specified port.
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*
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* @param port I2C port
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* @param slave_addr Slave address, with LSB set for receive-mode
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*
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* @return Non-zero if error.
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*/
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static int send_start(int port, uint16_t slave_addr_8bit)
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{
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int rv;
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/* Send start bit */
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_START;
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dump_i2c_reg(port, "sent start");
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rv = wait_sr1(port, STM32_I2C_SR1_SB);
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if (rv)
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return I2C_ERROR_FAILED_START;
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/* Write slave address */
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STM32_I2C_DR(port) = slave_addr_8bit & 0xff;
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rv = wait_sr1(port, STM32_I2C_SR1_ADDR);
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if (rv)
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return rv;
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/* Read SR2 to clear ADDR bit */
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rv = STM32_I2C_SR2(port);
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dump_i2c_reg(port, "wrote addr");
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return EC_SUCCESS;
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}
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static void i2c_set_freq_port(const struct i2c_port_t *p)
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{
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int port = p->port;
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int freq = clock_get_freq();
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/* Force peripheral reset and disable port */
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STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST;
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STM32_I2C_CR1(port) = 0;
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/* Set clock frequency */
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STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
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STM32_I2C_CR2(port) = freq / SECOND;
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STM32_I2C_TRISE(port) = freq / SECOND + 1;
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/* Enable port */
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
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}
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/**
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* Initialize on the specified I2C port.
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*
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* @param p the I2c port
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*/
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static void i2c_init_port(const struct i2c_port_t *p)
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{
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int port = p->port;
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/* Enable clocks to I2C modules if necessary */
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if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
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STM32_RCC_APB1ENR |= 1 << (21 + port);
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/* Configure GPIOs */
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gpio_config_module(MODULE_I2C, 1);
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/* Set up initial bus frequencies */
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i2c_set_freq_port(p);
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}
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/*****************************************************************************/
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/* Interface */
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int chip_i2c_xfer(const int port,
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const uint16_t slave_addr_flags,
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const uint8_t *out, int out_bytes,
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uint8_t *in, int in_bytes, int flags)
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{
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int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
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int started = (flags & I2C_XFER_START) ? 0 : 1;
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int rv = EC_SUCCESS;
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int i;
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ASSERT(out || !out_bytes);
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ASSERT(in || !in_bytes);
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dump_i2c_reg(port, "xfer start");
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/*
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* Clear status
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*
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* TODO(crosbug.com/p/29314): should check for any leftover error
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* status, and reset the port if present.
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*/
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STM32_I2C_SR1(port) = 0;
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/* Clear start, stop, POS, ACK bits to get us in a known state */
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STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
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STM32_I2C_CR1_STOP |
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STM32_I2C_CR1_POS |
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STM32_I2C_CR1_ACK);
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/* No out bytes and no in bytes means just check for active */
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if (out_bytes || !in_bytes) {
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if (!started) {
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rv = send_start(port, addr_8bit);
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if (rv)
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goto xfer_exit;
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}
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/* Write data, if any */
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for (i = 0; i < out_bytes; i++) {
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/* Write next data byte */
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STM32_I2C_DR(port) = out[i];
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dump_i2c_reg(port, "wrote data");
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rv = wait_sr1(port, STM32_I2C_SR1_BTF);
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if (rv)
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goto xfer_exit;
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}
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/* Need repeated start condition before reading */
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started = 0;
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/* If no input bytes, queue stop condition */
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if (!in_bytes && (flags & I2C_XFER_STOP))
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
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}
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if (in_bytes) {
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/* Setup ACK/POS before sending start as per user manual */
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if (in_bytes == 2)
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS;
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else if (in_bytes != 1)
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK;
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if (!started) {
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rv = send_start(port, addr_8bit | 0x01);
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if (rv)
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goto xfer_exit;
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}
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if (in_bytes == 1) {
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/* Set stop immediately after ADDR cleared */
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if (flags & I2C_XFER_STOP)
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
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rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
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if (rv)
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goto xfer_exit;
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in[0] = STM32_I2C_DR(port);
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} else if (in_bytes == 2) {
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/* Wait till the shift register is full */
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rv = wait_sr1(port, STM32_I2C_SR1_BTF);
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if (rv)
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goto xfer_exit;
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if (flags & I2C_XFER_STOP)
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
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in[0] = STM32_I2C_DR(port);
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in[1] = STM32_I2C_DR(port);
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} else {
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/* Read all but last three */
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for (i = 0; i < in_bytes - 3; i++) {
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/* Wait for receive buffer not empty */
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rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
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if (rv)
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goto xfer_exit;
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dump_i2c_reg(port, "read data");
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in[i] = STM32_I2C_DR(port);
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dump_i2c_reg(port, "post read data");
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}
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/* Wait for BTF (data N-2 in DR, N-1 in shift) */
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rv = wait_sr1(port, STM32_I2C_SR1_BTF);
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if (rv)
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goto xfer_exit;
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/* No more acking */
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STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
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in[i++] = STM32_I2C_DR(port);
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/* Wait for BTF (data N-1 in DR, N in shift) */
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rv = wait_sr1(port, STM32_I2C_SR1_BTF);
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if (rv)
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goto xfer_exit;
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/* If this is the last byte, queue stop condition */
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if (flags & I2C_XFER_STOP)
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
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/* Read the last two bytes */
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in[i++] = STM32_I2C_DR(port);
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in[i++] = STM32_I2C_DR(port);
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}
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}
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xfer_exit:
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/* On error, queue a stop condition */
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if (rv) {
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flags |= I2C_XFER_STOP;
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
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dump_i2c_reg(port, "stop after error");
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/*
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* If failed at sending start, try resetting the port
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* to unwedge the bus.
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*/
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if (rv == I2C_ERROR_FAILED_START) {
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const struct i2c_port_t *p = i2c_ports;
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CPRINTS("chip_i2c_xfer start error; "
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"unwedging and resetting i2c %d", port);
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i2c_unwedge(port);
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for (i = 0; i < i2c_ports_used; i++, p++) {
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if (p->port == port) {
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i2c_init_port(p);
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break;
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}
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}
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}
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}
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/* If a stop condition is queued, wait for it to take effect */
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if (flags & I2C_XFER_STOP) {
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/* Wait up to 100 us for bus idle */
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for (i = 0; i < 10; i++) {
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if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY))
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break;
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udelay(10);
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}
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/*
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* Allow bus to idle for at least one 100KHz clock = 10 us.
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* This allows slaves on the bus to detect bus-idle before
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* the next start condition.
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*/
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udelay(10);
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}
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return rv;
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}
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int i2c_raw_get_scl(int port)
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{
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enum gpio_signal g;
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if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
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return gpio_get_level(g);
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/* If no SCL pin defined for this port, then return 1 to appear idle. */
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return 1;
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}
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int i2c_raw_get_sda(int port)
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{
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enum gpio_signal g;
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if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
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return gpio_get_level(g);
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/* If no SCL pin defined for this port, then return 1 to appear idle. */
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return 1;
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}
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int i2c_get_line_levels(int port)
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{
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return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
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(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
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}
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|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/* Hooks */
|
||
|
|
|
||
|
|
/* Handle CPU clock changing frequency */
|
||
|
|
static void i2c_freq_change(void)
|
||
|
|
{
|
||
|
|
const struct i2c_port_t *p = i2c_ports;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < i2c_ports_used; i++, p++)
|
||
|
|
i2c_set_freq_port(p);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void i2c_pre_freq_change_hook(void)
|
||
|
|
{
|
||
|
|
const struct i2c_port_t *p = i2c_ports;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
/* Lock I2C ports so freq change can't interrupt an I2C transaction */
|
||
|
|
for (i = 0; i < i2c_ports_used; i++, p++)
|
||
|
|
i2c_lock(p->port, 1);
|
||
|
|
}
|
||
|
|
DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
|
||
|
|
static void i2c_freq_change_hook(void)
|
||
|
|
{
|
||
|
|
const struct i2c_port_t *p = i2c_ports;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
i2c_freq_change();
|
||
|
|
|
||
|
|
/* Unlock I2C ports we locked in pre-freq change hook */
|
||
|
|
for (i = 0; i < i2c_ports_used; i++, p++)
|
||
|
|
i2c_lock(p->port, 0);
|
||
|
|
}
|
||
|
|
DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
|
||
|
|
|
||
|
|
static void i2c_init(void)
|
||
|
|
{
|
||
|
|
const struct i2c_port_t *p = i2c_ports;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < i2c_ports_used; i++, p++)
|
||
|
|
i2c_init_port(p);
|
||
|
|
}
|
||
|
|
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);
|
||
|
|
|
||
|
|
/*****************************************************************************/
|
||
|
|
/* Console commands */
|
||
|
|
|
||
|
|
static int command_i2cdump(int argc, char **argv)
|
||
|
|
{
|
||
|
|
dump_i2c_reg(I2C_PORT_MASTER, "dump");
|
||
|
|
return EC_SUCCESS;
|
||
|
|
}
|
||
|
|
DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump,
|
||
|
|
NULL,
|
||
|
|
"Dump I2C regs");
|