466 lines
12 KiB
C
466 lines
12 KiB
C
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "printf.h"
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#include "chipset.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "i2c.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_I2C, outstr)
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#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
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/* Transmit timeout in microseconds */
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#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
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#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
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#define I2C_SLAVE_ERROR_CODE 0xec
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#if (I2C_PORT_EC == STM32_I2C1_PORT)
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#define IRQ_SLAVE STM32_IRQ_I2C1
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#else
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#define IRQ_SLAVE STM32_IRQ_I2C2
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#endif
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#endif
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/* I2C port state data */
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struct i2c_port_data {
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uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
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enum i2c_freq freq; /* Port clock speed */
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};
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static struct i2c_port_data pdata[I2C_PORT_COUNT];
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void i2c_set_timeout(int port, uint32_t timeout)
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{
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pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
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}
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/* timing register values for supported input clks / i2c clk rates */
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static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
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[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
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[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
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[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
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};
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/**
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* Wait for ISR register to contain the specified mask.
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*
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* Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
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* EC_ERROR_UNKNOWN if an error bit appeared in the status register.
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*/
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static int wait_isr(int port, int mask)
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{
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uint32_t start = __hw_clock_source_read();
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uint32_t delta = 0;
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do {
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int isr = STM32_I2C_ISR(port);
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/* Check for errors */
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if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
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STM32_I2C_ISR_NACK))
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return EC_ERROR_UNKNOWN;
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/* Check for desired mask */
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if ((isr & mask) == mask)
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return EC_SUCCESS;
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delta = __hw_clock_source_read() - start;
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/**
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* Depending on the bus speed, busy loop for a while before
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* sleeping and letting other things run.
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*/
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if (delta >= busyloop_us[pdata[port].freq])
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usleep(100);
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} while (delta < pdata[port].timeout_us);
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return EC_ERROR_TIMEOUT;
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}
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/* We are only using sysclk, which is 40MHZ */
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enum stm32_i2c_clk_src {
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I2C_CLK_SRC_40MHZ = 0,
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I2C_CLK_SRC_COUNT,
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};
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/* timing register values for supported input clks / i2c clk rates
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*
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* These values are calculated using ST's STM32cubeMX tool
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*/
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static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
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[I2C_CLK_SRC_40MHZ] = {
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[I2C_FREQ_1000KHZ] = 0x00100618,
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[I2C_FREQ_400KHZ] = 0x00301347,
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[I2C_FREQ_100KHZ] = 0x003087FF,
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},
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};
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static void i2c_set_freq_port(const struct i2c_port_t *p,
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enum stm32_i2c_clk_src src,
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enum i2c_freq freq)
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{
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int port = p->port;
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const uint32_t *regs = timingr_regs[src];
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/* Disable port */
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STM32_I2C_CR1(port) = 0;
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STM32_I2C_CR2(port) = 0;
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/* Set clock frequency */
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STM32_I2C_TIMINGR(port) = regs[freq];
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/* Enable port */
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STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
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pdata[port].freq = freq;
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}
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/**
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* Initialize on the specified I2C port.
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*
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* @param p the I2c port
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*/
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static void i2c_init_port(const struct i2c_port_t *p)
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{
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int port = p->port;
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uint32_t mask;
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uint8_t shift;
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enum stm32_i2c_clk_src src = I2C_CLK_SRC_40MHZ;
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enum i2c_freq freq;
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/* Enable clocks to I2C modules if necessary */
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if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
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STM32_RCC_APB1ENR |= 1 << (21 + port);
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/* Select sysclk as source */
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mask = STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2);
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shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + (port * 2);
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STM32_RCC_CCIPR &= ~mask;
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STM32_RCC_CCIPR |= STM32_RCC_CCIPR_I2C_SYSCLK << shift;
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/* Configure GPIOs */
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gpio_config_module(MODULE_I2C, 1);
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/* Set clock frequency */
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switch (p->kbps) {
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case 1000:
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freq = I2C_FREQ_1000KHZ;
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break;
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case 400:
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freq = I2C_FREQ_400KHZ;
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break;
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case 100:
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freq = I2C_FREQ_100KHZ;
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break;
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default: /* unknown speed, defaults to 100kBps */
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CPRINTS("I2C bad speed %d kBps", p->kbps);
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freq = I2C_FREQ_100KHZ;
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}
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/* Set up initial bus frequencies */
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i2c_set_freq_port(p, src, freq);
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/* Set up default timeout */
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i2c_set_timeout(port, 0);
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}
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/*****************************************************************************/
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#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
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static void i2c_event_handler(int port)
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{
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/* Variables tracking the handler state.
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* TODO: Should have as many sets of these variables as the number
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* of slave ports.
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*/
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static int rx_pending, rx_idx;
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static int tx_pending, tx_idx, tx_end;
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static uint8_t slave_buffer[I2C_MAX_HOST_PACKET_SIZE + 2];
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int isr = STM32_I2C_ISR(port);
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/*
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* Check for error conditions. Note, arbitration loss and bus error
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* are the only two errors we can get as a slave allowing clock
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* stretching and in non-SMBus mode.
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*/
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if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
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rx_pending = 0;
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tx_pending = 0;
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/* Make sure TXIS interrupt is disabled */
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STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
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/* Clear error status bits */
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STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
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| STM32_I2C_ICR_ARLOCF;
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}
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/* Transfer matched our slave address */
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if (isr & STM32_I2C_ISR_ADDR) {
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if (isr & STM32_I2C_ISR_DIR) {
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/* Transmitter slave */
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/* Clear transmit buffer */
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STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
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if (rx_pending)
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/* RESTART */
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i2c_data_received(port, slave_buffer, rx_idx);
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tx_end = i2c_set_response(port, slave_buffer, rx_idx);
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tx_idx = 0;
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rx_pending = 0;
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tx_pending = 1;
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/* Enable txis interrupt to start response */
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STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
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} else {
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/* Receiver slave */
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rx_idx = 0;
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rx_pending = 1;
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tx_pending = 0;
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}
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/* Clear ADDR bit by writing to ADDRCF bit */
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STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
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/* Inhibit stop mode when addressed until STOPF flag is set */
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disable_sleep(SLEEP_MASK_I2C_SLAVE);
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}
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/*
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* Receive buffer not empty
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*
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* When a master finishes sending data, it'll set STOP bit. It causes
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* the slave to receive RXNE and STOP interrupt at the same time. So,
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* we need to process RXNE first, then handle STOP.
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*/
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if (isr & STM32_I2C_ISR_RXNE)
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slave_buffer[rx_idx++] = STM32_I2C_RXDR(port);
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/* Stop condition on bus */
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if (isr & STM32_I2C_ISR_STOP) {
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if (rx_pending)
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i2c_data_received(port, slave_buffer, rx_idx);
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tx_idx = 0;
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tx_end = 0;
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rx_pending = 0;
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tx_pending = 0;
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/* Make sure TXIS interrupt is disabled */
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STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
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/* Clear STOPF bit by writing to STOPCF bit */
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STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
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/* No longer inhibit deep sleep after stop condition */
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enable_sleep(SLEEP_MASK_I2C_SLAVE);
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}
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if (isr & STM32_I2C_ISR_NACK) {
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/* Make sure TXIS interrupt is disabled */
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STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
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/* Clear NACK */
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STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
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}
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/* Transmitter empty event */
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if (isr & STM32_I2C_ISR_TXIS) {
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if (port == I2C_PORT_EC) {
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if (tx_pending) {
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if (tx_idx < tx_end) {
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STM32_I2C_TXDR(port) =
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slave_buffer[tx_idx++];
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} else {
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STM32_I2C_TXDR(port)
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= I2C_SLAVE_ERROR_CODE;
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tx_idx = 0;
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tx_end = 0;
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tx_pending = 0;
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}
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} else {
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STM32_I2C_TXDR(port) = I2C_SLAVE_ERROR_CODE;
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}
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}
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}
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}
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void i2c_event_interrupt(void)
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{
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i2c_event_handler(I2C_PORT_EC);
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}
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DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
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#endif
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/*****************************************************************************/
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/* Interface */
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int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
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const uint8_t *out, int out_bytes,
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uint8_t *in, int in_bytes, int flags)
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{
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int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
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int rv = EC_SUCCESS;
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int i;
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int xfer_start = flags & I2C_XFER_START;
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int xfer_stop = flags & I2C_XFER_STOP;
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ASSERT(out || !out_bytes);
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ASSERT(in || !in_bytes);
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/* Clear status */
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if (xfer_start) {
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STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
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STM32_I2C_CR2(port) = 0;
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}
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if (out_bytes || !in_bytes) {
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/*
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* Configure the write transfer: if we are stopping then set
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* AUTOEND bit to automatically set STOP bit after NBYTES.
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* if we are not stopping, set RELOAD bit so that we can load
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* NBYTES again. if we are starting, then set START bit.
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*/
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STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16)
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| addr_8bit
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| ((in_bytes == 0 && xfer_stop) ?
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STM32_I2C_CR2_AUTOEND : 0)
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| ((in_bytes == 0 && !xfer_stop) ?
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STM32_I2C_CR2_RELOAD : 0)
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| (xfer_start ? STM32_I2C_CR2_START : 0);
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for (i = 0; i < out_bytes; i++) {
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rv = wait_isr(port, STM32_I2C_ISR_TXIS);
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if (rv)
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goto xfer_exit;
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/* Write next data byte */
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STM32_I2C_TXDR(port) = out[i];
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}
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}
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if (in_bytes) {
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if (out_bytes) { /* wait for completion of the write */
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rv = wait_isr(port, STM32_I2C_ISR_TC);
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if (rv)
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goto xfer_exit;
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}
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/*
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* Configure the read transfer: if we are stopping then set
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* AUTOEND bit to automatically set STOP bit after NBYTES.
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|
|
* if we are not stopping, set RELOAD bit so that we can load
|
||
|
|
* NBYTES again. if we were just transmitting, we need to
|
||
|
|
* set START bit to send (re)start and begin read transaction.
|
||
|
|
*/
|
||
|
|
STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
|
||
|
|
| STM32_I2C_CR2_RD_WRN | addr_8bit
|
||
|
|
| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
|
||
|
|
| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
|
||
|
|
| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
|
||
|
|
|
||
|
|
for (i = 0; i < in_bytes; i++) {
|
||
|
|
/* Wait for receive buffer not empty */
|
||
|
|
rv = wait_isr(port, STM32_I2C_ISR_RXNE);
|
||
|
|
if (rv)
|
||
|
|
goto xfer_exit;
|
||
|
|
|
||
|
|
in[i] = STM32_I2C_RXDR(port);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If we are stopping, then we already set AUTOEND and we should
|
||
|
|
* wait for the stop bit to be transmitted. Otherwise, we set
|
||
|
|
* the RELOAD bit and we should wait for transfer complete
|
||
|
|
* reload (TCR).
|
||
|
|
*/
|
||
|
|
rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
|
||
|
|
if (rv)
|
||
|
|
goto xfer_exit;
|
||
|
|
|
||
|
|
xfer_exit:
|
||
|
|
/* clear status */
|
||
|
|
if (xfer_stop)
|
||
|
|
STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
|
||
|
|
|
||
|
|
/* On error, queue a stop condition */
|
||
|
|
if (rv) {
|
||
|
|
/* queue a STOP condition */
|
||
|
|
STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
|
||
|
|
/* wait for it to take effect */
|
||
|
|
/* Wait up to 100 us for bus idle */
|
||
|
|
for (i = 0; i < 10; i++) {
|
||
|
|
if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
|
||
|
|
break;
|
||
|
|
udelay(10);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allow bus to idle for at least one 100KHz clock = 10 us.
|
||
|
|
* This allows slaves on the bus to detect bus-idle before
|
||
|
|
* the next start condition.
|
||
|
|
*/
|
||
|
|
udelay(10);
|
||
|
|
/* re-initialize the controller */
|
||
|
|
STM32_I2C_CR2(port) = 0;
|
||
|
|
STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
|
||
|
|
udelay(10);
|
||
|
|
STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
|
||
|
|
}
|
||
|
|
|
||
|
|
return rv;
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_raw_get_scl(int port)
|
||
|
|
{
|
||
|
|
enum gpio_signal g;
|
||
|
|
|
||
|
|
if (get_scl_from_i2c_port(port, &g))
|
||
|
|
/* If no SCL pin is defined, return 1 to appear idle. */
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
return gpio_get_level(g);
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_raw_get_sda(int port)
|
||
|
|
{
|
||
|
|
enum gpio_signal g;
|
||
|
|
|
||
|
|
if (get_sda_from_i2c_port(port, &g))
|
||
|
|
/* If no SDA pin is defined, return 1 to appear idle. */
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
return gpio_get_level(g);
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_get_line_levels(int port)
|
||
|
|
{
|
||
|
|
return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
|
||
|
|
(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void i2c_init(void)
|
||
|
|
{
|
||
|
|
const struct i2c_port_t *p = i2c_ports;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < i2c_ports_used; i++, p++)
|
||
|
|
i2c_init_port(p);
|
||
|
|
|
||
|
|
#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
|
||
|
|
STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
|
||
|
|
| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
|
||
|
|
| STM32_I2C_CR1_NACKIE;
|
||
|
|
STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
|
||
|
|
| (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1);
|
||
|
|
task_enable_irq(IRQ_SLAVE);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);
|