67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
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/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Watchdog driver */
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "watchdog.h"
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/*
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* LSI oscillator frequency is typically 38 kHz, but it may be between 28-56
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* kHz and we don't calibrate it to know. Use 56 kHz so that we pick a counter
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* value large enough that we reload before the worst-case watchdog delay
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* (fastest LSI clock).
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*/
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#define LSI_CLOCK 56000
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/*
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* Use largest prescaler divider = /256. This gives a worst-case watchdog
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* clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) =
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* 18.7 sec.
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*/
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#define IWDG_PRESCALER 6
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#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER)
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void watchdog_reload(void)
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{
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/* Reload the watchdog */
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STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
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#ifdef CONFIG_WATCHDOG_HELP
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hwtimer_reset_watchdog();
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#endif
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}
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DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
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int watchdog_init(void)
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{
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/* Unlock watchdog registers */
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STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
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/* Set the prescaler between the LSI clock and the watchdog counter */
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STM32_IWDG_PR = IWDG_PRESCALER & 7;
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/* Set the reload value of the watchdog counter */
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STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
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(LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
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/* Start the watchdog (and re-lock registers) */
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STM32_IWDG_KR = STM32_IWDG_KR_START;
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#ifdef CONFIG_WATCHDOG_HELP
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/* Use a harder timer to warn about an impending watchdog reset */
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hwtimer_setup_watchdog();
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#endif
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return EC_SUCCESS;
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}
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