387 lines
8.8 KiB
ArmAsm
387 lines
8.8 KiB
ArmAsm
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* ISH minute-IA CPU initialization
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*/
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#include "config.h"
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#include "interrupts.h"
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#include "ia_structs.h"
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.equ CR0_NW, (1 << 29)
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.equ CR0_CD, (1 << 30)
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.global __idt
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.global __gdt
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.global __gdt_ptr
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# GDT is loaded by ISH ROM. The FW code retains the same GDT
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# and hence the same segment selector
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.set code_seg, 0x8
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.section .data.vecttable
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# Macro that defines an interrupt descriptor
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.macro interrupt_descriptor
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.word def_irq_low # low 16 bits of default_int_handler
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.word code_seg
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.byte 0
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.byte IDT_DESC_FLAGS
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.word def_irq_high # high 16 bits of default_int_handler
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.endm
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.align 32
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# Static Interrupt descriptor table (vectors 0-255), all vectors initialized
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# to default_int_handler. DECLARE_IRQ() remaps to the appropriate handler.
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__idt:
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interrupt_descriptor # 0 - Divide error
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interrupt_descriptor # 1 - Debug
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interrupt_descriptor # 2 - NMI interrupt
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interrupt_descriptor # 3 - Breakpoint
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interrupt_descriptor # 4 - Overflow
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interrupt_descriptor # 5 - Bound range exceeded
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interrupt_descriptor # 6 - Invalid opcode
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interrupt_descriptor # 7 - Device not available
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interrupt_descriptor # 8 - Double fault
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interrupt_descriptor # 9 - Coprocessor overrun
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interrupt_descriptor # 10 - Invalid TSS
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interrupt_descriptor # 11 - Segment not present
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interrupt_descriptor # 12 - Stack segment fault
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interrupt_descriptor # 13 - General protection
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interrupt_descriptor # 14 - Page fault
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interrupt_descriptor # 15 - Reserved
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interrupt_descriptor # 16 - Floating point error
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interrupt_descriptor # 17 - Alignment check
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interrupt_descriptor # 18 - Machine check
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interrupt_descriptor # 19 - SIMD floating-point exception
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interrupt_descriptor # 20 - Virtualization exception
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interrupt_descriptor # 21..31 - Reserved
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 32..255 - User-defined, Maskable Interrupts
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 64
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 96
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 128
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 160
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 192
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 224
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor
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interrupt_descriptor # 255
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__gdt:
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# Entry 0: Null descriptor
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.long 0x0
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.long 0x0
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# Entry 1: Code descriptor
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# Base: 0x0
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# Limit: 0xffffffff
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# Flags: 0x9b (Code E/R, Present, DPL0, Acessed=1)
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.long GEN_GDT_DESC_LO(0x0, 0xffffffff, GDT_DESC_CODE_FLAGS)
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.long GEN_GDT_DESC_UP(0x0, 0xffffffff, GDT_DESC_CODE_FLAGS)
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# Entry 2: Data descriptor
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# Base: 0x0
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# Limit: 0xffffffff
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# Flags: 0x93 (Data R/W, Present, DPL0, Acessed=1)
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.long GEN_GDT_DESC_LO(0x0, 0xffffffff, GDT_DESC_DATA_FLAGS)
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.long GEN_GDT_DESC_UP(0x0, 0xffffffff, GDT_DESC_DATA_FLAGS)
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#if defined(CONFIG_ISH_PM_AONTASK)
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# placeholder entries, will be updated by init_aon_task()
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# in power_mgt.c
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# Entry 3: placeholder TSS descriptor for main FW
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.long 0x0
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.long 0x0
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# Entry 4: placeholder TSS descriptor for aontask
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.long 0x0
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.long 0x0
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# Entry 5: placeholder LDT descriptor for aontask
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.long 0x0
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.long 0x0
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#endif
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#.section .data
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__idt_ptr:
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.word 2047 # Table size in bytes, count from 0
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# (8N - 1). N = 256 - the number of vectors
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.long __idt # Base address of IDT
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__gdt_ptr:
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.word 24
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.long __gdt
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.section .init
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.code32
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# The .init section is mapped to linear address 0xFF000000, the SRAM start.
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# ISH BUP (bring-up) downloads ISH FW to ISH SRAM and jumps to start address.
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.global reset
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# Entry point - core is already set to 32-bit linear mode by ISH ROM
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reset:
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# Disabling interrupts initially. It will be enabled when tasks start
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cli
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# Clear .bss section.
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xorl %eax, %eax
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cld
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movl $__bss_start, %edi
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movl $__bss_size_words, %ecx
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rep stosl
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# System stack is within .bss, already cleared
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movl $stack_end, %esp
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# Load GDT
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lgdt __gdt_ptr
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# Load IDT
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lidt __idt_ptr
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# Enable cache (CR0)
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movl %cr0, %eax
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andl $~(CR0_CD | CR0_NW), %eax
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movl %eax, %cr0
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# Reset Task-Switched flag to prevent an ESC instruction such
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# as fninit, from triggering a Device-not-available fault
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clts
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#ifdef CONFIG_FPU
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fninit
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#endif
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# Jump to C code
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jmp main
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# Reserve space for system stack
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.section .bss.system_stack
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stack_start:
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.space CONFIG_STACK_SIZE, 0
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stack_end:
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.global stack_end
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