270 lines
6.6 KiB
ArmAsm
270 lines
6.6 KiB
ArmAsm
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* N8 CPU initialization
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*/
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#include "config.h"
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/* magic macro to implement IRQ prefix / exit */
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.macro vector name, entry_number
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.weak \name\()_handler
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.set \name\()_handler, unhandled_irq
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j __entry_\()\name
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.pushsection .text.vectirq
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.global __entry_\()\name
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__entry_\()\name:
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/* the context is stored on the current task stack*/
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/* save r15, fp, lp and sp */
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smw.adm $r15, [$sp], $r15, 0xb
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/* r0-r5 are caller saved */
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smw.adm $r0, [$sp], $r5, 0
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/* store link pointer register */
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swi.gp $lp, [ + ilp]
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/* switch to system stack if we are called from process stack */
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la $r3, stack_end
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mov55 $fp, $sp
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slt45 $r3, $sp /* if sp > end of system stack, then r15 = 1 and */
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cmovn $sp, $r3, $r15 /* point sp to the top of the system stack */
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/* save entry number of HW interrupt */
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movi55 $r3, \entry_number\()
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swi.gp $r3, [ + cpu_int_entry_number]
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/* isr entry */
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jal start_irq_handler
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/* C routine handler */
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jal \name\()_handler
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/* check whether we need to change the scheduled task */
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lwi.gp $r2, [ + need_resched]
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bnez $r2, __switch_task
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/* isr exit */
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jal end_irq_handler
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/* restore r0-r5 */
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lmw.bim $r0, [$fp], $r5, 0
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/* restore r15, fp, lp and sp */
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lmw.bi $r15, [$fp], $r15, 0xb
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/* restore PC and PSW */
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iret
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.popsection
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.pushsection .rodata.vecthandlers
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.long \name\()_handler
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.popsection
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.endm
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.section .text.vecttable
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/* Exceptions vector */
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vectors:
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j reset /* reset / NMI */
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j excep_handler /* TLB fill */
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j excep_handler /* PTE not present */
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j excep_handler /* TLB misc */
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j excep_handler /* TLB VLPT miss */
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j excep_handler /* Machine error */
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j excep_handler /* Debug related */
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j excep_handler /* General exception */
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vector syscall, -1 /* Syscall */
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vector irq_0, 0 /* HW 0 */
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vector irq_1, 1 /* HW 1 */
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vector irq_2, 2 /* HW 2 */
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vector irq_3, 3 /* HW 3 */
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vector irq_4, 4 /* HW 4 */
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vector irq_5, 5 /* HW 5 */
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vector irq_6, 6 /* HW 6 */
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vector irq_7, 7 /* HW 7 */
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vector irq_8, 8 /* HW 8 */
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vector irq_9, 9 /* HW 9 */
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vector irq_10, 10 /* HW 10 */
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vector irq_11, 11 /* HW 11 */
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vector irq_12, 12 /* HW 12 */
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vector irq_13, 13 /* HW 13 */
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vector irq_14, 14 /* HW 14 */
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vector irq_15, 15 /* HW 15 */
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/* E-flash signature */
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.org 0x80
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.balign 16
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.global eflash_sig
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eflash_sig:
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.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
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#ifdef CONFIG_HOSTCMD_ESPI
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.byte 0xA4 /* eSPI */
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#else
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.byte 0xA5 /* LPC */
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#endif
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.byte 0xB4 /* flag of signature */
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.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
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/* flags: internal oscillator + implicit location */
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.text
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.global reset
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reset:
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/*
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* GIE (global interrupt) is always disabled here. the first
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* "iret" instruction of syscall interrupt (triggered by __task_start)
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* will restore PSW from IPSW, and will enable GIE.
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* Firmware will not change GIE settings (set/clear) until the next
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* reset, unless there's an interrupt event.
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* When there is an interrupt event, N8 CPU will save PSW register to
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* IPSW register and clear GIE then jump to interrupt service routine.
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* N8 will restore PSW from IPSW after "iret" instruction.
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*/
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setgie.d
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dsb
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/* GP register is used to access .data and .bss */
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la $gp, _SDA_BASE_
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/* Set system stack pointer. */
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la $sp, stack_end
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/*
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* move content of lp into r5 and then store the content
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* into variable "ec_reset_lp" later after memory initialization.
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*/
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mov55 $r5, $lp
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/* map/enable the 16kB of DLM at 0x00080000 */
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li $r0, 0x00080005
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mtsr $r0, $mr7
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/* Set ROM address at 0x80000 (disabled). */
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li $r1, 0x00F0109B
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movi $r0, #0x8
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sbi $r0, [$r1]
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/* Enable DLM 8k~12K(bit2) and DLM 12k~16k(bit3) */
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li $r1, 0x00F02030
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lbi $r0, [$r1]
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ori $r0, $r0, 0x0C
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sbi $r0, [$r1]
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/* Enable DLM 16k~36K bit[2-6] */
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li $r1, 0x00F0203E
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lbi $r0, [$r1]
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ori $r0, $r0, 0x7C
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sbi $r0, [$r1]
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/* Enable DLM 36k~48K bit[0-2] */
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li $r1, 0x00F02044
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lbi $r0, [$r1]
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ori $r0, $r0, 0x7
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sbi $r0, [$r1]
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/* Clear BSS */
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la $r0, _bss_start
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lwi $r1, [$r0]
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la $r0, _bss_end
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lwi $r2, [$r0]
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movi $r0, #0
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bss_loop:
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swi.bi $r0, [$r1], 4
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bne $r1, $r2, bss_loop
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/* Copy initialized data to DLM */
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la $r0, _data_start
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lwi $r1, [$r0]
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la $r0, _data_end
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lwi $r2, [$r0]
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la $r0, _data_lma_start
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lwi $r0, [$r0]
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data_loop:
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lwi.bi $r3, [$r0], 4
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swi.bi $r3, [$r1], 4
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bne $r1, $r2, data_loop
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/* store the content of r5 (lp after reset) into "ec_reset_lp" */
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swi.gp $r5, [ + ec_reset_lp]
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/* we switch to our own exception vectors */
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/* go back to it level 0 with HW interrupts globally disabled */
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li $r4, 0x70008
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mtsr $r4, $PSW
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/* IT8380 specific: set vectors at 0 */
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li $r5, 0x0F02041 /* IVTBAR in GCTRL */
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movi $r15, 0
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sbi $r15, [$r5]
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/* Interrupt vectors are every 4 bytes */
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li $r5, 0x00000007
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mtsr $r5, $IVB
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/* clear BRAM if it is not valid */
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jal chip_bram_valid
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/* Jump to C routine */
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jal main
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/* That should not return. If it does, loop forever. */
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j .
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.global unhandled_irq
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unhandled_irq:
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mfsr $gp, $ITYPE
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sethi $r15, 0xBAD0
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or $r15, $r15, $gp
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mtsr $r15, $ITYPE
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dsb
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j excep_handler /* display exception with ITYPE=bad00<irq> */
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.global excep_handler
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excep_handler:
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#ifdef CONFIG_FPU
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/*
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* We have to restore ALU so that we can continue the next
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* sequence if arithmetic instructions are used.
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* (Apply to floating point division by zero)
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*/
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sethi $gp, 0x80
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ori $gp, $gp,0x9
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mtsr $gp, $dlmb
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dsb
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#endif
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/* safety: reload GP even though it should be already set */
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la $gp, _SDA_BASE_
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/* save r0 to free one register */
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swi.gp $r0, [ + saved_regs]
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/* save the remaining 15 registers */
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la $r0, saved_regs + 4
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smw.bim $r1, [$r0], $r10, 0
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smw.bim $r15,[$r0], $r15, 0xF
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/* put a sane stack pointer */
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la $sp, stack_end
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/* add IPC, IPSW to the context */
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mfsr $r1, $IPC
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mfsr $r2, $IPSW
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smw.bi $r1, [$r0], $r2, 0
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/* pass ir6/ITYPE as the second parameter */
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mfsr $r1, $ITYPE
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/* exception context pointer as first parameter */
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addi $r0, $r0, -16*4
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/* jump to panic dump C routine */
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jal report_panic
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/* we never return: exceptions are fatal */
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j .
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.align 2
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_bss_start:
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.long __bss_start
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_bss_end:
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.long __bss_end
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_data_start:
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.long __data_start
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_data_end:
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.long __data_end
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_data_lma_start:
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.long __data_lma_start
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/* Reserve space for system stack */
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.section .bss.system_stack
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stack_start:
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.space CONFIG_STACK_SIZE, 0
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stack_end:
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.global stack_end
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/* registers state at exception entry */
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.global saved_regs
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saved_regs:
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.long 0, 0, 0, 0, 0, 0, 0, 0
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.long 0, 0, 0, 0, 0, 0, 0, 0
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/* IPC, IPSW for convenient access */
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.long 0, 0
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