110 lines
3.6 KiB
C
110 lines
3.6 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USB Power delivery port management */
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#ifndef __CROS_EC_DRIVER_TCPM_IT83XX_H
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#define __CROS_EC_DRIVER_TCPM_IT83XX_H
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/*
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* Dedicated setting for CC pin.
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* This setting will connect CC pin to internal PD module directly without
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* applying any GPIO/ALT configuration.
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*/
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#define IT83XX_USBPD_CC_PIN_CONFIG 0x86
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#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM_BIT(PD_EVENT_FIRST_FREE_BIT)
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#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask))
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#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask)))
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#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0)
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#define IS_MASK_CLEAR(reg, bit_mask) (((reg) & (bit_mask)) == 0)
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/* macros for set */
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#define USBPD_KICK_TX_START(port) \
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SET_MASK(IT83XX_USBPD_MTCR(port), \
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USBPD_REG_MASK_TX_START)
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#define USBPD_SEND_HARD_RESET(port) \
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SET_MASK(IT83XX_USBPD_MTSR0(port), \
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USBPD_REG_MASK_SEND_HW_RESET)
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#define USBPD_SW_RESET(port) \
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SET_MASK(IT83XX_USBPD_GCR(port), \
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USBPD_REG_MASK_SW_RESET_BIT)
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#define USBPD_ENABLE_BMC_PHY(port) \
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SET_MASK(IT83XX_USBPD_GCR(port), \
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USBPD_REG_MASK_BMC_PHY)
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#define USBPD_DISABLE_BMC_PHY(port) \
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CLEAR_MASK(IT83XX_USBPD_GCR(port), \
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USBPD_REG_MASK_BMC_PHY)
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#define USBPD_START(port) \
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CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
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USBPD_REG_MASK_DISABLE_CC)
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#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \
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SET_MASK(IT83XX_USBPD_MTSR0(port), \
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USBPD_REG_MASK_SEND_BIST_MODE_2)
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#define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
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CLEAR_MASK(IT83XX_USBPD_MTSR0(port), \
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USBPD_REG_MASK_SEND_BIST_MODE_2)
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/* macros for get */
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#define USBPD_GET_POWER_ROLE(port) \
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(IT83XX_USBPD_PDMSR(port) & 1)
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#define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
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(IT83XX_USBPD_CCGCR(port) & BIT(1))
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#define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
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(IT83XX_USBPD_BMCSR(port) & BIT(3))
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#define USBPD_GET_PULL_CC_SELECTION(port) \
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(IT83XX_USBPD_CCGCR(port) & 1)
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/* macros for check */
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#define USBPD_IS_TX_ERR(port) \
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IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_ERR_STAT)
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#define USBPD_IS_TX_DISCARD(port) \
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IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_DISCARD_STAT)
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/* macros for PD ISR */
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#define USBPD_IS_HARD_RESET_DETECT(port) \
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IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT)
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#define USBPD_IS_TX_DONE(port) \
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IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE)
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#define USBPD_IS_RX_DONE(port) \
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IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_RX_DONE)
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#ifdef IT83XX_INTC_PLUG_IN_SUPPORT
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#define USBPD_IS_PLUG_IN_OUT_DETECT(port)\
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IS_MASK_SET(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_IN_OUT_DETECT_STAT)
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#endif //IT83XX_INTC_PLUG_IN_SUPPORT
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enum usbpd_ufp_volt_status {
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USBPD_UFP_STATE_SNK_OPEN = 0,
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USBPD_UFP_STATE_SNK_DEF = 1,
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USBPD_UFP_STATE_SNK_1_5 = 3,
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USBPD_UFP_STATE_SNK_3_0 = 7,
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};
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enum usbpd_dfp_volt_status {
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USBPD_DFP_STATE_SRC_RA = 0,
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USBPD_DFP_STATE_SRC_RD = 1,
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USBPD_DFP_STATE_SRC_OPEN = 3,
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};
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enum usbpd_power_role {
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USBPD_POWER_ROLE_CONSUMER,
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USBPD_POWER_ROLE_PROVIDER,
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USBPD_POWER_ROLE_CONSUMER_PROVIDER,
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USBPD_POWER_ROLE_PROVIDER_CONSUMER,
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};
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struct usbpd_ctrl_t {
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volatile uint8_t *cc1;
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volatile uint8_t *cc2;
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uint8_t irq;
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};
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extern const struct usbpd_ctrl_t usbpd_ctrl_regs[];
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extern const struct tcpm_drv it83xx_tcpm_drv;
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/* Disable integrated pd module */
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void it83xx_disable_pd_module(int port);
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#endif /* __CROS_EC_DRIVER_TCPM_IT83XX_H */
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