53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Apollolake chipset power control module for Chrome EC */
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#ifndef __CROS_EC_APOLLOLAKE_H
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#define __CROS_EC_APOLLOLAKE_H
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/*
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* Input state flags.
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* TODO: Normalize the power signal masks from board defines to SoC headers.
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*/
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#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N)
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#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
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#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N)
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#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N)
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#define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N
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#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
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#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N)
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#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \
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IN_SLP_S4_N)
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#define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
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#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
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#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
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#define CHARGER_INITIALIZED_DELAY_MS 100
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#define CHARGER_INITIALIZED_TRIES 40
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enum power_signal {
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#ifdef CONFIG_POWER_S0IX
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X86_SLP_S0_N, /* PCH -> SLP_S0_L */
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#endif
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X86_SLP_S3_N, /* PCH -> SLP_S3_L */
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X86_SLP_S4_N, /* PCH -> SLP_S4_L */
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X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */
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X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */
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X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */
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X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */
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X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */
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/* Number of X86 signals */
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POWER_SIGNAL_COUNT
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};
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#endif /* __CROS_EC_APOLLOLAKE_H */
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