322 lines
7.8 KiB
C
322 lines
7.8 KiB
C
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/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* X86 braswell chipset power control module for Chrome EC */
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#include "chipset.h"
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#include "common.h"
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#include "console.h"
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#include "ec_commands.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "lid_switch.h"
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#include "lpc.h"
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#include "power.h"
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#include "power_button.h"
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#include "system.h"
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#include "timer.h"
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#include "usb_charge.h"
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#include "util.h"
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#include "wireless.h"
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#include "registers.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
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#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
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/* Input state flags */
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#define IN_RSMRST_L_PWRGD POWER_SIGNAL_MASK(X86_RSMRST_L_PWRGD)
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#define IN_ALL_SYS_PWRGD POWER_SIGNAL_MASK(X86_ALL_SYS_PWRGD)
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#define IN_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
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#define IN_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
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/* All always-on supplies */
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#define IN_PGOOD_ALWAYS_ON (IN_RSMRST_L_PWRGD)
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/* All non-core power rails */
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#define IN_PGOOD_ALL_NONCORE (IN_ALL_SYS_PWRGD)
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/* All core power rails */
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#define IN_PGOOD_ALL_CORE (IN_ALL_SYS_PWRGD)
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/* Rails required for S5 */
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#define IN_PGOOD_S5 (IN_PGOOD_ALWAYS_ON)
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/* Rails required for S3 */
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#define IN_PGOOD_S3 (IN_PGOOD_ALWAYS_ON)
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/* Rails required for S0 */
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#define IN_PGOOD_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
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/* All PM_SLP signals from PCH deasserted */
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#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
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/* All inputs in the right state for S0 */
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#define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED)
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static int throttle_cpu; /* Throttle CPU? */
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static int forcing_shutdown; /* Forced shutdown in progress? */
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void chipset_force_shutdown(enum chipset_shutdown_reason reason)
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{
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CPRINTS("%s(%d)", __func__, reason);
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report_ap_reset(reason);
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/*
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* Force power off. This condition will reset once the state machine
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* transitions to G3.
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*/
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#ifndef CONFIG_PMIC
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gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
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#endif
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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forcing_shutdown = 1;
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}
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void chipset_reset(enum chipset_reset_reason reason)
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{
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CPRINTS("%s: %d", __func__, reason);
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report_ap_reset(reason);
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/*
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* Send a reset pulse to the PCH. This just causes it to
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* assert INIT# to the CPU without dropping power or asserting
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* PLTRST# to reset the rest of the system. The PCH uses a 16
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* ms debounce time, so assert the signal for twice that.
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*/
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gpio_set_level(GPIO_PCH_RCIN_L, 0);
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usleep(32 * MSEC);
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gpio_set_level(GPIO_PCH_RCIN_L, 1);
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}
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void chipset_throttle_cpu(int throttle)
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{
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#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
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throttle = !throttle;
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#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
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if (chipset_in_state(CHIPSET_STATE_ON))
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gpio_set_level(GPIO_CPU_PROCHOT, throttle);
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}
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enum power_state power_chipset_init(void)
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{
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/* Pause in S5 when shutting down. */
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power_set_pause_in_s5(1);
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/*
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* If we're switching between images without rebooting, see if the x86
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* is already powered on; if so, leave it there instead of cycling
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* through G3.
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*/
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if (system_jumped_to_this_image()) {
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if ((power_get_signals() & IN_PGOOD_S0) == IN_PGOOD_S0) {
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/* Disable idle task deep sleep when in S0. */
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disable_sleep(SLEEP_MASK_AP_RUN);
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CPRINTS("already in S0");
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return POWER_S0;
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} else {
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/* Force all signals to their G3 states */
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CPRINTS("forcing G3");
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gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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/*wireless_set_state(WIRELESS_OFF);*/
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}
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}
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return POWER_G3;
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}
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enum power_state power_handle_state(enum power_state state)
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{
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switch (state) {
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case POWER_G3:
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break;
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case POWER_G3S5:
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/* Exit SOC G3 */
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#ifdef CONFIG_PMIC
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gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
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#else
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gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0);
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#endif
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CPRINTS("Exit SOC G3");
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if (power_wait_signals(IN_PGOOD_S5)) {
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chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
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return POWER_G3;
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}
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/* Deassert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 1);
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return POWER_S5;
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case POWER_S5:
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/* Check for SLP S4 */
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if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
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return POWER_S5S3; /* Power up to next state */
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break;
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case POWER_S5S3:
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/* Call hooks now that rails are up */
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hook_notify(HOOK_CHIPSET_STARTUP);
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return POWER_S3;
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case POWER_S3:
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/* Check for state transitions */
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if (!power_has_signals(IN_PGOOD_S3)) {
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/* Required rail went away */
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chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
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return POWER_S3S5;
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} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
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/* Power up to next state */
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return POWER_S3S0;
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} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
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/* Power down to next state */
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return POWER_S3S5;
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}
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break;
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case POWER_S3S0:
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/* Enable wireless */
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/*wireless_set_state(WIRELESS_ON);*/
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if (!power_has_signals(IN_PGOOD_S3)) {
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chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
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/*wireless_set_state(WIRELESS_OFF);*/
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return POWER_S3S5;
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}
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/* Call hooks now that rails are up */
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hook_notify(HOOK_CHIPSET_RESUME);
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/*
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* Disable idle task deep sleep. This means that the low
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* power idle task will not go into deep sleep while in S0.
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*/
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disable_sleep(SLEEP_MASK_AP_RUN);
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/*
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* Wait 15 ms after all voltages good. 100 ms is only needed
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* for PCIe devices; mini-PCIe devices should need only 10 ms.
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*/
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msleep(15);
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/*
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* Throttle CPU if necessary. This should only be asserted
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* when +VCCP is powered (it is by now).
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*/
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#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
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gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu);
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#else
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gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
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#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
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/* Set SYS and CORE PWROK */
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gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
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return POWER_S0;
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case POWER_S0:
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if (!power_has_signals(IN_PGOOD_ALWAYS_ON)) {
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chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
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return POWER_S0S3;
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}
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if (!power_has_signals(IN_ALL_S0)) {
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return POWER_S0S3;
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}
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break;
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case POWER_S0S3:
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/* Call hooks before we remove power rails */
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hook_notify(HOOK_CHIPSET_SUSPEND);
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#ifndef CONFIG_PMIC
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/* Clear SYS and CORE PWROK */
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gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
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#endif
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/* Wait 40ns */
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udelay(1);
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/* Suspend wireless */
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/*wireless_set_state(WIRELESS_SUSPEND);*/
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/*
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* Enable idle task deep sleep. Allow the low power idle task
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* to go into deep sleep in S3 or lower.
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*/
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enable_sleep(SLEEP_MASK_AP_RUN);
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/*
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* Deassert prochot since CPU is off and we're about to drop
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* +VCCP.
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*/
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gpio_set_level(GPIO_CPU_PROCHOT, 0);
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return POWER_S3;
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case POWER_S3S5:
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/* Call hooks before we remove power rails */
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hook_notify(HOOK_CHIPSET_SHUTDOWN);
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/*wireless_set_state(WIRELESS_OFF);*/
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/* Start shutting down */
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return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
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case POWER_S5G3:
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/*
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* in case shutdown is already done by apshutdown
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* (or chipset_force_shutdown()), SOC already lost
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* power and can't assert PMC_SUSPWRDNACK any more.
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*/
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if (forcing_shutdown) {
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/* Config pins for SOC G3 */
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gpio_config_module(MODULE_GPIO, 1);
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#ifndef CONFIG_PMIC
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gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
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#else
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gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
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#endif
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forcing_shutdown = 0;
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CPRINTS("Enter SOC G3");
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return POWER_G3;
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}
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if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) {
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/* Assert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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/* Config pins for SOC G3 */
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gpio_config_module(MODULE_GPIO, 1);
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/* Enter SOC G3 */
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#ifdef CONFIG_PMIC
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gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
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udelay(1);
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gpio_set_level(GPIO_PCH_RSMRST_L, 0);
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#else
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gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
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#endif
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CPRINTS("Enter SOC G3");
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return POWER_G3;
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} else {
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CPRINTS("waiting for PMC_SUSPWRDNACK to assert!");
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return POWER_S5;
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}
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}
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return state;
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}
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