31 lines
1.0 KiB
C
31 lines
1.0 KiB
C
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Cannonlake chipset power control module for Chrome EC */
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#ifndef __CROS_EC_CANNONLAKE_H
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#define __CROS_EC_CANNONLAKE_H
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/* Input state flags. */
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#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
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#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
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#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
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#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
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IN_PCH_SLP_S4_DEASSERTED | \
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IN_PCH_SLP_SUS_DEASSERTED)
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#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
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#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
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PP5000_PGOOD_POWER_SIGNAL_MASK)
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#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
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#define CHARGER_INITIALIZED_DELAY_MS 100
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#define CHARGER_INITIALIZED_TRIES 40
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#endif /* __CROS_EC_CANNONLAKE_H */
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