282 lines
10 KiB
Ada
282 lines
10 KiB
Ada
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--
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-- Copyright (C) 2015-2016 secunet Security Networks AG
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-- Copyright (C) 2016 Nico Huber <nico.h@gmx.de>
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.GFX.GMA.Config;
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with HW.GFX.GMA.DP_Info;
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with HW.GFX.GMA.Registers;
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with HW.Debug;
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with GNAT.Source_Info;
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package body HW.GFX.GMA.PCH.Transcoder is
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type DPLL_SEL_Array is array (FDI_Port_Type) of Word32;
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DPLL_SEL_TRANSCODER_x_DPLL_ENABLE : constant DPLL_SEL_Array :=
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(FDI_A => 1 * 2 ** 3,
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FDI_B => 1 * 2 ** 7,
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FDI_C => 1 * 2 ** 11);
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DPLL_SEL_TRANSCODER_x_DPLL_SEL_MASK : constant DPLL_SEL_Array :=
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(FDI_A => 1 * 2 ** 0,
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FDI_B => 1 * 2 ** 4,
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FDI_C => 1 * 2 ** 8);
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function DPLL_SEL_TRANSCODER_x_DPLL_SEL
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(Port : FDI_Port_Type;
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PLL : Word32)
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return Word32
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is
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begin
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return Shift_Left (PLL,
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(case Port is
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when FDI_A => 0,
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when FDI_B => 4,
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when FDI_C => 8));
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end DPLL_SEL_TRANSCODER_x_DPLL_SEL;
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TRANS_CONF_TRANSCODER_ENABLE : constant := 1 * 2 ** 31;
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TRANS_CONF_TRANSCODER_STATE : constant := 1 * 2 ** 30;
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TRANS_CHICKEN2_TIMING_OVERRIDE : constant := 1 * 2 ** 31;
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TRANS_DP_CTL_OUTPUT_ENABLE : constant := 1 * 2 ** 31;
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TRANS_DP_CTL_PORT_SELECT_MASK : constant := 3 * 2 ** 29;
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TRANS_DP_CTL_PORT_SELECT_NONE : constant := 3 * 2 ** 29;
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TRANS_DP_CTL_ENHANCED_FRAMING : constant := 1 * 2 ** 18;
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TRANS_DP_CTL_VSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 4;
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TRANS_DP_CTL_HSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 3;
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type TRANS_DP_CTL_PORT_SELECT_Array is array (PCH_Port) of Word32;
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TRANS_DP_CTL_PORT_SELECT : constant TRANS_DP_CTL_PORT_SELECT_Array :=
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(PCH_DP_B => 0 * 2 ** 29,
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PCH_DP_C => 1 * 2 ** 29,
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PCH_DP_D => 2 * 2 ** 29,
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others => 0);
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function TRANS_DP_CTL_BPC (BPC : BPC_Type) return Word32
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is
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begin
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return
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(case BPC is
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when 6 => 2 * 2 ** 9,
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when 10 => 1 * 2 ** 9,
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when 12 => 3 * 2 ** 9,
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when others => 0 * 2 ** 9);
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end TRANS_DP_CTL_BPC;
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function TRANS_DATA_M_TU (Transfer_Unit : Positive) return Word32 is
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begin
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return Shift_Left (Word32 (Transfer_Unit - 1), 25);
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end TRANS_DATA_M_TU;
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----------------------------------------------------------------------------
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type Transcoder_Registers is record
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HTOTAL : Registers.Registers_Index;
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HBLANK : Registers.Registers_Index;
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HSYNC : Registers.Registers_Index;
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VTOTAL : Registers.Registers_Index;
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VBLANK : Registers.Registers_Index;
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VSYNC : Registers.Registers_Index;
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CONF : Registers.Registers_Index;
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DP_CTL : Registers.Registers_Index;
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DATA_M : Registers.Registers_Index;
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DATA_N : Registers.Registers_Index;
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LINK_M : Registers.Registers_Index;
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LINK_N : Registers.Registers_Index;
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CHICKEN2 : Registers.Registers_Index;
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end record;
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type Transcoder_Registers_Array is
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array (FDI_Port_Type) of Transcoder_Registers;
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TRANS : constant Transcoder_Registers_Array := Transcoder_Registers_Array'
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(FDI_A =>
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(HTOTAL => Registers.TRANS_HTOTAL_A,
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HBLANK => Registers.TRANS_HBLANK_A,
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HSYNC => Registers.TRANS_HSYNC_A,
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VTOTAL => Registers.TRANS_VTOTAL_A,
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VBLANK => Registers.TRANS_VBLANK_A,
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VSYNC => Registers.TRANS_VSYNC_A,
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CONF => Registers.TRANSACONF,
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DP_CTL => Registers.TRANS_DP_CTL_A,
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DATA_M => Registers.TRANSA_DATA_M1,
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DATA_N => Registers.TRANSA_DATA_N1,
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LINK_M => Registers.TRANSA_DP_LINK_M1,
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LINK_N => Registers.TRANSA_DP_LINK_N1,
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CHICKEN2 => Registers.TRANSA_CHICKEN2),
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FDI_B =>
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(HTOTAL => Registers.TRANS_HTOTAL_B,
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HBLANK => Registers.TRANS_HBLANK_B,
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HSYNC => Registers.TRANS_HSYNC_B,
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VTOTAL => Registers.TRANS_VTOTAL_B,
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VBLANK => Registers.TRANS_VBLANK_B,
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VSYNC => Registers.TRANS_VSYNC_B,
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CONF => Registers.TRANSBCONF,
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DP_CTL => Registers.TRANS_DP_CTL_B,
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DATA_M => Registers.TRANSB_DATA_M1,
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DATA_N => Registers.TRANSB_DATA_N1,
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LINK_M => Registers.TRANSB_DP_LINK_M1,
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LINK_N => Registers.TRANSB_DP_LINK_N1,
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CHICKEN2 => Registers.TRANSB_CHICKEN2),
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FDI_C =>
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(HTOTAL => Registers.TRANS_HTOTAL_C,
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HBLANK => Registers.TRANS_HBLANK_C,
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HSYNC => Registers.TRANS_HSYNC_C,
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VTOTAL => Registers.TRANS_VTOTAL_C,
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VBLANK => Registers.TRANS_VBLANK_C,
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VSYNC => Registers.TRANS_VSYNC_C,
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CONF => Registers.TRANSCCONF,
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DP_CTL => Registers.TRANS_DP_CTL_C,
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DATA_M => Registers.TRANSC_DATA_M1,
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DATA_N => Registers.TRANSC_DATA_N1,
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LINK_M => Registers.TRANSC_DP_LINK_M1,
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LINK_N => Registers.TRANSC_DP_LINK_N1,
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CHICKEN2 => Registers.TRANSC_CHICKEN2));
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----------------------------------------------------------------------------
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procedure On
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(Port_Cfg : Port_Config;
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Port : FDI_Port_Type;
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PLL : Word32)
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is
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Mode : constant Mode_Type := Port_Cfg.Mode;
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function Encode (LSW, MSW : Pos32) return Word32 is
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begin
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return (Word32 (LSW) - 1) or ((Word32 (MSW) - 1) * 2 ** 16);
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end Encode;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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if Config.Has_DPLL_SEL then
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Registers.Unset_And_Set_Mask
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(Register => Registers.PCH_DPLL_SEL,
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Mask_Unset => DPLL_SEL_TRANSCODER_x_DPLL_SEL_MASK (Port),
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Mask_Set => DPLL_SEL_TRANSCODER_x_DPLL_ENABLE (Port) or
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DPLL_SEL_TRANSCODER_x_DPLL_SEL (Port, PLL));
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end if;
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Registers.Write
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(Register => TRANS (Port).HTOTAL,
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Value => Encode (Mode.H_Visible, Mode.H_Total));
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Registers.Write
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(Register => TRANS (Port).HBLANK,
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Value => Encode (Mode.H_Visible, Mode.H_Total));
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Registers.Write
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(Register => TRANS (Port).HSYNC,
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Value => Encode (Mode.H_Sync_Begin, Mode.H_Sync_End));
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Registers.Write
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(Register => TRANS (Port).VTOTAL,
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Value => Encode (Mode.V_Visible, Mode.V_Total));
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Registers.Write
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(Register => TRANS (Port).VBLANK,
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Value => Encode (Mode.V_Visible, Mode.V_Total));
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Registers.Write
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(Register => TRANS (Port).VSYNC,
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Value => Encode (Mode.V_Sync_Begin, Mode.V_Sync_End));
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if Port_Cfg.Display = DP then
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declare
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Data_M, Link_M : DP_Info.M_Type;
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Data_N, Link_N : DP_Info.N_Type;
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begin
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DP_Info.Calculate_M_N
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(Link => Port_Cfg.DP,
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Mode => Port_Cfg.Mode,
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Data_M => Data_M,
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Data_N => Data_N,
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Link_M => Link_M,
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Link_N => Link_N);
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Registers.Write
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(Register => TRANS (Port).DATA_M,
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Value => TRANS_DATA_M_TU (64) or
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Word32 (Data_M));
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Registers.Write
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(Register => TRANS (Port).DATA_N,
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Value => Word32 (Data_N));
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Registers.Write
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(Register => TRANS (Port).LINK_M,
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Value => Word32 (Link_M));
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Registers.Write
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(Register => TRANS (Port).LINK_N,
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Value => Word32 (Link_N));
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end;
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if Config.Has_Trans_DP_Ctl then
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declare
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Polarity : constant Word32 :=
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(if Port_Cfg.Mode.H_Sync_Active_High then
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TRANS_DP_CTL_HSYNC_ACTIVE_HIGH else 0) or
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(if Port_Cfg.Mode.V_Sync_Active_High then
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TRANS_DP_CTL_VSYNC_ACTIVE_HIGH else 0);
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Enhanced_Framing : constant Word32 :=
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(if Port_Cfg.DP.Enhanced_Framing then
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TRANS_DP_CTL_ENHANCED_FRAMING else 0);
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begin
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Registers.Write
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(Register => TRANS (Port).DP_CTL,
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Value => TRANS_DP_CTL_OUTPUT_ENABLE or
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TRANS_DP_CTL_PORT_SELECT (Port_Cfg.PCH_Port) or
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Enhanced_Framing or
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TRANS_DP_CTL_BPC (Port_Cfg.Mode.BPC) or
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Polarity);
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end;
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end if;
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end if;
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if Config.Has_Trans_Timing_Ovrrde then
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Registers.Set_Mask
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(Register => TRANS (Port).CHICKEN2,
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Mask => TRANS_CHICKEN2_TIMING_OVERRIDE);
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end if;
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Registers.Write
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(Register => TRANS (Port).CONF,
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Value => TRANS_CONF_TRANSCODER_ENABLE);
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end On;
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procedure Off (Port : FDI_Port_Type) is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_Mask
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(Register => TRANS (Port).CONF,
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Mask => TRANS_CONF_TRANSCODER_ENABLE);
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Registers.Wait_Unset_Mask
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(Register => TRANS (Port).CONF,
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Mask => TRANS_CONF_TRANSCODER_STATE,
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TOut_MS => 50);
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if Config.Has_Trans_Timing_Ovrrde then
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Registers.Unset_Mask
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(Register => TRANS (Port).CHICKEN2,
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Mask => TRANS_CHICKEN2_TIMING_OVERRIDE);
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end if;
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if Config.Has_Trans_DP_Ctl then
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Registers.Write
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(Register => TRANS (Port).DP_CTL,
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Value => TRANS_DP_CTL_PORT_SELECT_NONE);
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end if;
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if Config.Has_DPLL_SEL then
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Registers.Unset_Mask
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(Register => Registers.PCH_DPLL_SEL,
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Mask => DPLL_SEL_TRANSCODER_x_DPLL_ENABLE (Port));
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end if;
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end Off;
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end HW.GFX.GMA.PCH.Transcoder;
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