405 lines
9.0 KiB
C
405 lines
9.0 KiB
C
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_fp.h>
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#include <sbi/riscv_locks.h>
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#include <sbi/sbi_bits.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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/**
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* Return HART ID of the caller.
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*/
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unsigned int sbi_current_hartid()
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{
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return (u32)csr_read(CSR_MHARTID);
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}
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static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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/* Enable FPU */
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if (misa_extension('D') || misa_extension('F'))
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csr_write(CSR_MSTATUS, MSTATUS_FS);
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/* Enable user/supervisor use of perf counters */
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if (misa_extension('S') && sbi_platform_has_scounteren(plat))
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csr_write(CSR_SCOUNTEREN, -1);
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if (sbi_platform_has_mcounteren(plat))
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csr_write(CSR_MCOUNTEREN, -1);
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/* Disable all interrupts */
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csr_write(CSR_MIE, 0);
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/* Disable S-mode paging */
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if (misa_extension('S'))
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csr_write(CSR_SATP, 0);
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}
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static int fp_init(u32 hartid)
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{
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#ifdef __riscv_flen
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int i;
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#endif
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if (!misa_extension('D') && !misa_extension('F'))
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return 0;
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if (!(csr_read(CSR_MSTATUS) & MSTATUS_FS))
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return SBI_EINVAL;
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#ifdef __riscv_flen
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for (i = 0; i < 32; i++)
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init_fp_reg(i);
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csr_write(CSR_FCSR, 0);
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#endif
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return 0;
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}
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static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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unsigned long interrupts, exceptions;
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if (!misa_extension('S'))
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/* No delegation possible as mideleg does not exist*/
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return 0;
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/* Send M-mode interrupts and most exceptions to S-mode */
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interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
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exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
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(1U << CAUSE_USER_ECALL);
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if (sbi_platform_has_mfaults_delegation(plat))
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exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) |
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(1U << CAUSE_LOAD_PAGE_FAULT) |
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(1U << CAUSE_STORE_PAGE_FAULT);
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/*
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* If hypervisor extension available then we only handle
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* hypervisor calls (i.e. ecalls from HS-mode) and we let
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* HS-mode handle supervisor calls (i.e. ecalls from VS-mode)
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*/
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if (misa_extension('H'))
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exceptions |= (1U << CAUSE_SUPERVISOR_ECALL);
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csr_write(CSR_MIDELEG, interrupts);
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csr_write(CSR_MEDELEG, exceptions);
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if (csr_read(CSR_MIDELEG) != interrupts)
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return SBI_EFAIL;
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if (csr_read(CSR_MEDELEG) != exceptions)
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return SBI_EFAIL;
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return 0;
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}
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unsigned long log2roundup(unsigned long x)
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{
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unsigned long ret = 0;
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while (ret < __riscv_xlen) {
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if (x <= (1UL << ret))
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break;
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ret++;
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}
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return ret;
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}
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void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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unsigned long prot, addr, size, l2l;
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unsigned int i;
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if (!sbi_platform_has_pmp(plat))
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return;
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for (i = 0; i < PMP_COUNT; i++) {
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pmp_get(i, &prot, &addr, &l2l);
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if (!(prot & PMP_A))
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continue;
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if (l2l < __riscv_xlen)
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size = (1UL << l2l);
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else
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size = 0;
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#if __riscv_xlen == 32
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sbi_printf("PMP%d: 0x%08lx-0x%08lx (A",
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#else
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sbi_printf("PMP%d: 0x%016lx-0x%016lx (A",
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#endif
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i, addr, addr + size - 1);
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if (prot & PMP_L)
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sbi_printf(",L");
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if (prot & PMP_R)
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sbi_printf(",R");
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if (prot & PMP_W)
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sbi_printf(",W");
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if (prot & PMP_X)
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sbi_printf(",X");
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sbi_printf(")\n");
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}
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}
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static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
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{
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u32 i, count;
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unsigned long fw_start, fw_size_log2;
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ulong prot, addr, log2size;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (!sbi_platform_has_pmp(plat))
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return 0;
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fw_size_log2 = log2roundup(scratch->fw_size);
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fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
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pmp_set(0, 0, fw_start, fw_size_log2);
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count = sbi_platform_pmp_region_count(plat, hartid);
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if ((PMP_COUNT - 1) < count)
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count = (PMP_COUNT - 1);
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for (i = 0; i < count; i++) {
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if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
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&log2size))
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continue;
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pmp_set(i + 1, prot, addr, log2size);
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}
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return 0;
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}
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static unsigned long trap_info_offset;
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int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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trap_info_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
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"HART_TRAP_INFO");
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if (!trap_info_offset)
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return SBI_ENOMEM;
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}
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mstatus_init(scratch, hartid);
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rc = fp_init(hartid);
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if (rc)
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return rc;
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rc = delegate_traps(scratch, hartid);
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if (rc)
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return rc;
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return pmp_init(scratch, hartid);
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}
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void *sbi_hart_get_trap_info(struct sbi_scratch *scratch)
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{
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unsigned long *trap_info;
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if (!trap_info_offset)
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return NULL;
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trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
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return (void *)(*trap_info);
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}
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void sbi_hart_set_trap_info(struct sbi_scratch *scratch, void *data)
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{
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unsigned long *trap_info;
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if (!trap_info_offset)
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return;
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trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
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*trap_info = (unsigned long)data;
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}
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void __attribute__((noreturn)) sbi_hart_hang(void)
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{
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while (1)
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wfi();
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__builtin_unreachable();
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}
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void __attribute__((noreturn))
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sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
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unsigned long next_addr, unsigned long next_mode,
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bool next_virt)
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{
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#if __riscv_xlen == 32
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unsigned long val, valH;
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#else
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unsigned long val;
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#endif
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switch (next_mode) {
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case PRV_M:
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break;
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case PRV_S:
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if (!misa_extension('S'))
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sbi_hart_hang();
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break;
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case PRV_U:
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if (!misa_extension('U'))
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sbi_hart_hang();
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break;
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default:
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sbi_hart_hang();
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}
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val = csr_read(CSR_MSTATUS);
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val = INSERT_FIELD(val, MSTATUS_MPP, next_mode);
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val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
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#if __riscv_xlen == 32
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if (misa_extension('H')) {
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valH = csr_read(CSR_MSTATUSH);
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valH = INSERT_FIELD(valH, MSTATUSH_MTL, 0);
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if (next_virt)
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valH = INSERT_FIELD(valH, MSTATUSH_MPV, 1);
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else
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valH = INSERT_FIELD(valH, MSTATUSH_MPV, 0);
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csr_write(CSR_MSTATUSH, valH);
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}
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#else
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if (misa_extension('H')) {
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val = INSERT_FIELD(val, MSTATUS_MTL, 0);
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if (next_virt)
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val = INSERT_FIELD(val, MSTATUS_MPV, 1);
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else
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val = INSERT_FIELD(val, MSTATUS_MPV, 0);
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}
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#endif
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csr_write(CSR_MSTATUS, val);
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csr_write(CSR_MEPC, next_addr);
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if (next_mode == PRV_S) {
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csr_write(CSR_STVEC, next_addr);
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csr_write(CSR_SSCRATCH, 0);
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csr_write(CSR_SIE, 0);
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csr_write(CSR_SATP, 0);
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} else if (next_mode == PRV_U) {
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csr_write(CSR_UTVEC, next_addr);
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csr_write(CSR_USCRATCH, 0);
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csr_write(CSR_UIE, 0);
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}
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register unsigned long a0 asm("a0") = arg0;
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register unsigned long a1 asm("a1") = arg1;
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__asm__ __volatile__("mret" : : "r"(a0), "r"(a1));
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__builtin_unreachable();
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}
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static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
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static volatile unsigned long avail_hart_mask = 0;
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void sbi_hart_mark_available(u32 hartid)
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{
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spin_lock(&avail_hart_mask_lock);
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avail_hart_mask |= (1UL << hartid);
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spin_unlock(&avail_hart_mask_lock);
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}
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void sbi_hart_unmark_available(u32 hartid)
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{
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spin_lock(&avail_hart_mask_lock);
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avail_hart_mask &= ~(1UL << hartid);
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spin_unlock(&avail_hart_mask_lock);
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}
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ulong sbi_hart_available_mask(void)
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{
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ulong ret;
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spin_lock(&avail_hart_mask_lock);
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ret = avail_hart_mask;
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spin_unlock(&avail_hart_mask_lock);
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return ret;
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}
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typedef struct sbi_scratch *(*h2s)(ulong hartid);
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struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
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u32 hartid)
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{
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return ((h2s)scratch->hartid_to_scratch)(hartid);
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}
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#define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
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static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
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static unsigned long coldboot_done = 0;
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static unsigned long coldboot_wait_bitmap = 0;
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void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if ((sbi_platform_hart_count(plat) <= hartid) ||
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(COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
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sbi_hart_hang();
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/* Set MSIE bit to receive IPI */
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csr_set(CSR_MIE, MIP_MSIP);
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/* Acquire coldboot lock */
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spin_lock(&coldboot_lock);
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/* Mark current HART as waiting */
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coldboot_wait_bitmap |= (1UL << hartid);
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/* Wait for coldboot to finish using WFI */
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while (!coldboot_done) {
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spin_unlock(&coldboot_lock);
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wfi();
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spin_lock(&coldboot_lock);
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};
|
||
|
|
|
||
|
|
/* Unmark current HART as waiting */
|
||
|
|
coldboot_wait_bitmap &= ~(1UL << hartid);
|
||
|
|
|
||
|
|
/* Release coldboot lock */
|
||
|
|
spin_unlock(&coldboot_lock);
|
||
|
|
|
||
|
|
/* Clear current HART IPI */
|
||
|
|
sbi_platform_ipi_clear(plat, hartid);
|
||
|
|
}
|
||
|
|
|
||
|
|
void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
|
||
|
|
{
|
||
|
|
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||
|
|
int max_hart = sbi_platform_hart_count(plat);
|
||
|
|
|
||
|
|
/* Acquire coldboot lock */
|
||
|
|
spin_lock(&coldboot_lock);
|
||
|
|
|
||
|
|
/* Mark coldboot done */
|
||
|
|
coldboot_done = 1;
|
||
|
|
|
||
|
|
/* Send an IPI to all HARTs waiting for coldboot */
|
||
|
|
for (int i = 0; i < max_hart; i++) {
|
||
|
|
if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))
|
||
|
|
sbi_platform_ipi_send(plat, i);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Release coldboot lock */
|
||
|
|
spin_unlock(&coldboot_lock);
|
||
|
|
}
|