287 lines
8.9 KiB
C
287 lines
8.9 KiB
C
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_unpriv.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_illegal_insn.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_misaligned_ldst.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_trap.h>
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static void __noreturn sbi_trap_error(const char *msg, int rc, u32 hartid,
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ulong mcause, ulong mtval,
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struct sbi_trap_regs *regs)
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{
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sbi_printf("%s: hart%d: %s (error %d)\n", __func__, hartid, msg, rc);
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sbi_printf("%s: hart%d: mcause=0x%" PRILX " mtval=0x%" PRILX "\n",
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__func__, hartid, mcause, mtval);
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sbi_printf("%s: hart%d: mepc=0x%" PRILX " mstatus=0x%" PRILX "\n",
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__func__, hartid, regs->mepc, regs->mstatus);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "ra", regs->ra, "sp", regs->sp);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "gp", regs->gp, "tp", regs->tp);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s0", regs->s0, "s1", regs->s1);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "a0", regs->a0, "a1", regs->a1);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "a2", regs->a2, "a3", regs->a3);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "a4", regs->a4, "a5", regs->a5);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "a6", regs->a6, "a7", regs->a7);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s2", regs->s2, "s3", regs->s3);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s4", regs->s4, "s5", regs->s5);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s6", regs->s6, "s7", regs->s7);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s8", regs->s8, "s9", regs->s9);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "s10", regs->s10, "s11", regs->s11);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "t0", regs->t0, "t1", regs->t1);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "t2", regs->t2, "t3", regs->t3);
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sbi_printf("%s: hart%d: %s=0x%" PRILX " %s=0x%" PRILX "\n", __func__,
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hartid, "t4", regs->t4, "t5", regs->t5);
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sbi_printf("%s: hart%d: %s=0x%" PRILX "\n", __func__, hartid, "t6",
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regs->t6);
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sbi_hart_hang();
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}
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/**
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* Redirect trap to lower privledge mode (S-mode or U-mode)
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*
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* @param regs pointer to register state
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* @param scratch pointer to sbi_scratch of current HART
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* @param epc error PC for lower privledge mode
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* @param cause exception cause for lower privledge mode
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* @param tval trap value for lower privledge mode
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*
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* @return 0 on success and negative error code on failure
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*/
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int sbi_trap_redirect(struct sbi_trap_regs *regs, struct sbi_scratch *scratch,
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ulong epc, ulong cause, ulong tval)
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{
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ulong hstatus, vsstatus, prev_mode;
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#if __riscv_xlen == 32
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bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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bool prev_stage2 = (regs->mstatusH & MSTATUSH_MTL) ? TRUE : FALSE;
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#else
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bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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bool prev_stage2 = (regs->mstatus & MSTATUS_MTL) ? TRUE : FALSE;
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#endif
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/* By default, we redirect to HS-mode */
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bool next_virt = FALSE;
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/* Sanity check on previous mode */
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prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
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if (prev_mode != PRV_S && prev_mode != PRV_U)
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return SBI_ENOTSUPP;
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/* For certain exceptions from VS/VU-mode we redirect to VS-mode */
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if (misa_extension('H') && prev_virt && !prev_stage2) {
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switch (cause) {
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case CAUSE_FETCH_PAGE_FAULT:
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case CAUSE_LOAD_PAGE_FAULT:
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case CAUSE_STORE_PAGE_FAULT:
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next_virt = TRUE;
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break;
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default:
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break;
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};
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}
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/* Update MSTATUS MPV and MTL bits */
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#if __riscv_xlen == 32
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regs->mstatusH &= ~MSTATUSH_MPV;
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regs->mstatusH |= (next_virt) ? MSTATUSH_MPV : 0UL;
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regs->mstatusH &= ~MSTATUSH_MTL;
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#else
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regs->mstatus &= ~MSTATUS_MPV;
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regs->mstatus |= (next_virt) ? MSTATUS_MPV : 0UL;
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regs->mstatus &= ~MSTATUS_MTL;
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#endif
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/* Update HSTATUS for VS/VU-mode to HS-mode transition */
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if (misa_extension('H') && prev_virt && !next_virt) {
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/* Update HSTATUS SP2P, SP2V, SPV, and STL bits */
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hstatus = csr_read(CSR_HSTATUS);
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hstatus &= ~HSTATUS_SP2P;
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hstatus |= (regs->mstatus & MSTATUS_SPP) ? HSTATUS_SP2P : 0;
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hstatus &= ~HSTATUS_SP2V;
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hstatus |= (hstatus & HSTATUS_SPV) ? HSTATUS_SP2V : 0;
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hstatus &= ~HSTATUS_SPV;
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hstatus |= (prev_virt) ? HSTATUS_SPV : 0;
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hstatus &= ~HSTATUS_STL;
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hstatus |= (prev_stage2) ? HSTATUS_STL : 0;
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csr_write(CSR_HSTATUS, hstatus);
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}
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/* Update exception related CSRs */
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if (next_virt) {
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/* Update VS-mode exception info */
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csr_write(CSR_VSTVAL, tval);
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csr_write(CSR_VSEPC, epc);
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csr_write(CSR_VSCAUSE, cause);
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/* Set MEPC to VS-mode exception vector base */
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regs->mepc = csr_read(CSR_VSTVEC);
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/* Set MPP to VS-mode */
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regs->mstatus &= ~MSTATUS_MPP;
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regs->mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
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/* Get VS-mode SSTATUS CSR */
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vsstatus = csr_read(CSR_VSSTATUS);
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/* Set SPP for VS-mode */
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vsstatus &= ~SSTATUS_SPP;
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if (prev_mode == PRV_S)
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vsstatus |= (1UL << SSTATUS_SPP_SHIFT);
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/* Set SPIE for VS-mode */
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vsstatus &= ~SSTATUS_SPIE;
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if (vsstatus & SSTATUS_SIE)
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vsstatus |= (1UL << SSTATUS_SPIE_SHIFT);
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/* Clear SIE for VS-mode */
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vsstatus &= ~SSTATUS_SIE;
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/* Update VS-mode SSTATUS CSR */
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csr_write(CSR_VSSTATUS, vsstatus);
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} else {
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/* Update S-mode exception info */
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csr_write(CSR_STVAL, tval);
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csr_write(CSR_SEPC, epc);
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csr_write(CSR_SCAUSE, cause);
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/* Set MEPC to S-mode exception vector base */
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regs->mepc = csr_read(CSR_STVEC);
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/* Set MPP to S-mode */
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regs->mstatus &= ~MSTATUS_MPP;
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regs->mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
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/* Set SPP for S-mode*/
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regs->mstatus &= ~MSTATUS_SPP;
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if (prev_mode == PRV_S)
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regs->mstatus |= (1UL << MSTATUS_SPP_SHIFT);
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/* Set SPIE for S-mode */
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regs->mstatus &= ~MSTATUS_SPIE;
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if (regs->mstatus & MSTATUS_SIE)
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regs->mstatus |= (1UL << MSTATUS_SPIE_SHIFT);
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/* Clear SIE for S-mode */
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regs->mstatus &= ~MSTATUS_SIE;
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}
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return 0;
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}
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/**
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* Handle trap/interrupt
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*
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* This function is called by firmware linked to OpenSBI
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* library for handling trap/interrupt. It expects the
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* following:
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* 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
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* 2. The 'mcause' CSR is having exception/interrupt cause
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* 3. The 'mtval' CSR is having additional trap information
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* 4. Stack pointer (SP) is setup for current HART
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* 5. Interrupts are disabled in MSTATUS CSR
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*
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* @param regs pointer to register state
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* @param scratch pointer to sbi_scratch of current HART
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*/
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void sbi_trap_handler(struct sbi_trap_regs *regs, struct sbi_scratch *scratch)
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{
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int rc = SBI_ENOTSUPP;
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const char *msg = "trap handler failed";
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u32 hartid = sbi_current_hartid();
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ulong mcause = csr_read(CSR_MCAUSE);
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ulong mtval = csr_read(CSR_MTVAL);
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struct unpriv_trap *uptrap;
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if (mcause & (1UL << (__riscv_xlen - 1))) {
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mcause &= ~(1UL << (__riscv_xlen - 1));
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switch (mcause) {
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case IRQ_M_TIMER:
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sbi_timer_process(scratch);
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break;
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case IRQ_M_SOFT:
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sbi_ipi_process(scratch);
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break;
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default:
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msg = "unhandled external interrupt";
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goto trap_error;
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};
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return;
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}
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switch (mcause) {
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case CAUSE_ILLEGAL_INSTRUCTION:
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rc = sbi_illegal_insn_handler(hartid, mcause, regs, scratch);
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msg = "illegal instruction handler failed";
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break;
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case CAUSE_MISALIGNED_LOAD:
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rc = sbi_misaligned_load_handler(hartid, mcause, regs, scratch);
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msg = "misaligned load handler failed";
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break;
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case CAUSE_MISALIGNED_STORE:
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rc = sbi_misaligned_store_handler(hartid, mcause, regs,
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scratch);
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msg = "misaligned store handler failed";
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break;
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case CAUSE_SUPERVISOR_ECALL:
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case CAUSE_HYPERVISOR_ECALL:
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rc = sbi_ecall_handler(hartid, mcause, regs, scratch);
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msg = "ecall handler failed";
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break;
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case CAUSE_LOAD_ACCESS:
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case CAUSE_STORE_ACCESS:
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case CAUSE_LOAD_PAGE_FAULT:
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case CAUSE_STORE_PAGE_FAULT:
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uptrap = sbi_hart_get_trap_info(scratch);
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if ((regs->mstatus & MSTATUS_MPRV) && uptrap) {
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rc = 0;
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regs->mepc += uptrap->ilen;
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uptrap->cause = mcause;
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uptrap->tval = mtval;
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} else {
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rc = sbi_trap_redirect(regs, scratch, regs->mepc,
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mcause, mtval);
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}
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msg = "page/access fault handler failed";
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break;
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default:
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/* If the trap came from S or U mode, redirect it there */
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rc = sbi_trap_redirect(regs, scratch, regs->mepc,
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mcause, mtval);
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break;
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};
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trap_error:
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if (rc) {
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sbi_trap_error(msg, rc, hartid, mcause, csr_read(CSR_MTVAL),
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regs);
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}
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}
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