117 lines
4.9 KiB
Markdown
117 lines
4.9 KiB
Markdown
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# PC Engines APU2
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This page describes how to run coreboot on PC Engines APU2 platform.
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## Technology
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```eval_rst
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+------------+---------------------------------------------------------------+
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| CPU | AMD G series GX-412TC |
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+------------+---------------------------------------------------------------+
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| CPU core | 1 GHz quad Puma core with 64 bit support |
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| | 32K data + 32K instruction cache per core, shared 2MB L2 cache|
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+------------+---------------------------------------------------------------+
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| DRAM | 2 or 4 GB DDR3-1333 DRAM |
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+------------+---------------------------------------------------------------+
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| Boot | From SD card, USB, mSATA SSD, SATA |
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+------------+---------------------------------------------------------------+
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| Power | 6 to 12W of 12V power |
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+------------+---------------------------------------------------------------+
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| Firmware | coreboot with support for iPXE and USB boot |
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+------------+---------------------------------------------------------------+
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```
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## Required proprietary blobs
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To build working coreboot image some blobs are needed.
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| amdfw.rom* | AMD Platform Security Processor | Required |
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+-----------------+---------------------------------+---------------------+
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| AGESA.bin | AGESA Platform Initialization | Required |
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+-----------------+---------------------------------+---------------------+
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| xhci.bin | AMD XHCI controller | Optional |
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+-----------------+---------------------------------+---------------------+
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```
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(\*) - package containing all required blobs for PSP. Directory, in which all
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blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
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## Flashing coreboot
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```eval_rst
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+---------------------+--------------------------+
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| Type | Value |
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+=====================+==========================+
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| Socketed flash | no |
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+---------------------+--------------------------+
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| Model | W25Q64 |
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+---------------------+--------------------------+
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| Size | 8 MiB |
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+---------------------+--------------------------+
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| Package | SOIC-8 |
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+---------------------+--------------------------+
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| Write protection | jumper on WP# pin* |
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+---------------------+--------------------------+
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| Dual BIOS feature | no |
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+---------------------+--------------------------+
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| Internal flashing | yes |
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+---------------------+--------------------------+
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```
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(\*) - It is used in normal SPI mode, but can be dangerous when using Quad SPI
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Flash. Then, pull-down resistors should be considered rather than jumper.
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### Internal programming
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The SPI flash can be accessed using [flashrom].
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flashrom -p internal -w coreboot.rom
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### External programming
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**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5
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(Soft-off) power state. S5 state can be forced by shorting power button pin on
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J2 header.
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The external access to flash chip is available through standard SOP-8 clip or
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SOP-8 header next to the flash chip on the board. Notice that not all boards
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have a header soldered down originally. Hence, there could be an empty slot with
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8 eyelets, so you can solder down a header on your own. The SPI flash chip and
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SPI header are marked in the picture below. Also there is SPI header and SPI
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flash pin layout included. Depend on using header or clip there are important
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rules:
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- using header J6 - don't connect 1,7,8 pins
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- using clip U23 - don't connect 3,7,8 pins
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Also signatures at the schematic can be ambiguous:
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- J6 SPIDI = U23 SO = MISO
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- J6 SPIDO = U23 SI = MOSI
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There is no restrictions as to the programmer device. It is only recommended to
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flash firmware without supplying power. External programming can be performed,
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for example using OrangePi and Armbian. You can exploit linux_spi driver which
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provides communication with SPI devices. Example command to program SPI flash
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with OrangePi using linux_spi:
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flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000
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**apu2 platform with marked in SPI header and SPI flash chip**
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![][apu2_flash]
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**SPI header pin layout**
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![][spi_header]
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## Schematics
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PC Engines APU2 [platform schematics](https://pcengines.ch/schema/apu2d.pdf)
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are available for free on PC Engines official site. Both configurations
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(2GB/4GB) have the same PCB and schematic.
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[apu2_flash]: apu2.jpg
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[spi_header]: apu2_spi.jpg
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[flashrom]: https://flashrom.org/Flashrom
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