120 lines
2.7 KiB
Markdown
120 lines
2.7 KiB
Markdown
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# Cavium CN81xx documentation
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## Reference code
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```eval_rst
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The Cavium reference code is called `BDK`_ (board development kit) and is part
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of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot.
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```
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## SOC code
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The SOC folder contains functions for:
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* TWSI
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* UART
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* TIMER
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* SPI
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* MMU
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* DRAM
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* CLOCK
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* GPIO
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* Secondary CPUs
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* PCI
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All other hardware is initilized by the BDK code, which is invoked from
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ramstage.
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## Notes about the hardware
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Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the
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L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed
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location. It then jumps to the firmware.
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```eval_rst
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For more details have a look at `Cavium CN8XXX Bootflow`_.
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```
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## CAR setup
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For Cache-as-RAM we only need to lock the cachelines which are used by bootblock
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or romstage until DRAM has been set up. At the end of romstage the cachelines
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are unlocked and the contents are flushed to DRAM.
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Locked cachelines are never evicted.
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The CAR setup is done in `bootblock_custom.S` and thus doesn't use the common
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aarch64 `bootblock.S` code.
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## DRAM setup
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```eval_rst
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The DRAM setup is done by the `BDK`_.
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```
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## PCI setup
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The PCI setup is done using the MMCONF mechanism.
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Besides configuring device visibility (secure/unsecure) the MSI-X interrupts
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needs to be configured.
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## Devicetree patching
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The Linux devicetree needs to be patched, depending on the available hardware
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and their configuration. Some values depends on fuses, some on user selectable
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configuration.
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The following SoC specific fixes are made:
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1. Fix SCLK
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2. Fix UUA refclock
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3. Remove unused PEM entries
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4. Remove unused QLM entries
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5. Set local MAC address
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## CN81xx quirks
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The CN81xx needs some quirks that are not documented or hidden in the code.
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### Violation of PCI spec
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**Problem:**
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* The PCI device 01:01.0 is disabled, but a multifunction device.
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* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot
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PCI allocator.
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**Solution:**
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The PCI Bus 0 and 1 are scanned manually in SOC's PCI code.
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### Crash accessing SLI memory
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**Problem:**
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The SLI memory region decodes to attached PCIe devices.
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Accessing the memory region results in 'Data Abort Exception' if the link of the
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PCIe device never had been enabled.
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**Solution:**
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Enable the PCIe link at least once. (You can disabling the link and the SLI
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memory reads as 0xffffffff.)
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### RNG Data Abort Exception
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**Problem:**
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'Data Abort Exception' on accessing the enabled RNG.
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**Solution**:
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Read the BDK_RNM_CTL_STATUS register at least once after writing it.
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```eval_rst
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.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
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.. _Cavium CN8XXX Bootflow: ../bootflow.html
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.. _BDK: ../../../vendorcode/cavium/bdk.html
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```
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