310 lines
7.3 KiB
C
310 lines
7.3 KiB
C
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#define HAVE_STRING_SUPPORT 0
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#define HAVE_CAST_SUPPORT 0
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#define HAVE_STATIC_ARRAY_SUPPORT 0
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#define HAVE_POINTER_SUPPORT 0
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#define HAVE_CONSTANT_PROPOGATION 0
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void outb(unsigned char value, unsigned short port)
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{
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__builtin_outb(value, port);
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}
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void outw(unsigned short value, unsigned short port)
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{
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__builtin_outw(value, port);
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}
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void outl(unsigned int value, unsigned short port)
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{
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__builtin_outl(value, port);
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}
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unsigned char inb(unsigned short port)
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{
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return __builtin_inb(port);
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}
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unsigned char inw(unsigned short port)
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{
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return __builtin_inw(port);
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}
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unsigned char inl(unsigned short port)
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{
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return __builtin_inl(port);
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}
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static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
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{
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return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
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}
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static unsigned char pcibios_read_config_byte(
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unsigned char bus, unsigned devfn, unsigned where)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inb(0xCFC + (where & 3));
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}
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static unsigned short pcibios_read_config_word(
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unsigned char bus, unsigned devfn, unsigned where)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inw(0xCFC + (where & 2));
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}
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static unsigned int pcibios_read_config_dword(
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unsigned char bus, unsigned devfn, unsigned where)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inl(0xCFC);
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}
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static void pcibios_write_config_byte(
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unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outb(value, 0xCFC + (where & 3));
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}
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static void pcibios_write_config_word(
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unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outw(value, 0xCFC + (where & 2));
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}
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static void pcibios_write_config_dword(
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unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outl(value, 0xCFC);
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}
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int log2(int value)
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{
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/* __builtin_bsr is a exactly equivalent to the x86 machine
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* instruction with the exception that it returns -1
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* when the value presented to it is zero.
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* Otherwise __builtin_bsr returns the zero based index of
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* the highest bit set.
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*/
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return __builtin_bsr(value);
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}
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#define PIIX4_DEVFN 0x90
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#define SMBUS_MEM_DEVICE_START 0x50
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#define SMBUS_MEM_DEVICE_END 0x53
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#define SMBUS_MEM_DEVICE_INC 1
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#define PM_BUS 0
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#define PM_DEVFN (PIIX4_DEVFN+3)
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#if HAVE_CONSTANT_PROPOGATION
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#define SMBUS_IO_BASE 0x1000
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#define SMBHSTSTAT 0
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#define SMBHSTCTL 2
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#define SMBHSTCMD 3
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#define SMBHSTADD 4
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#define SMBHSTDAT0 5
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#define SMBHSTDAT1 6
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#define SMBBLKDAT 7
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static void smbus_wait_until_ready(void)
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{
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while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
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/* nop */
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}
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}
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static void smbus_wait_until_done(void)
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{
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unsigned char byte;
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do {
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byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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}while((byte &1) == 1);
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while( (byte & ~1) == 0) {
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byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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}
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}
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int smbus_read_byte(unsigned device, unsigned address)
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{
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unsigned char host_status_register;
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unsigned char byte;
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int result;
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smbus_wait_until_ready();
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/* setup transaction */
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/* disable interrupts */
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
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/* set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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/* clear the data byte...*/
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outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
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/* start the command */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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/* read results of transaction */
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byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
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result = byte;
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if (host_status_register != 0x02) {
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result = -1;
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}
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return result;
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}
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#else /* !HAVE_CONSTANT_PROPOGATION */
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#define SMBUS_IO_HSTSTAT 0x1000
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#define SMBUS_IO_HSTCTL 0x1002
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#define SMBUS_IO_HSTCMD 0x1003
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#define SMBUS_IO_HSTADD 0x1004
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#define SMBUS_IO_HSTDAT0 0x1005
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#define SMBUS_IO_HSTDAT1 0x1006
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#define SMBUS_IO_HSTBLKDAT 0x1007
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static void smbus_wait_until_ready(void)
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{
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while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) {
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/* nop */
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}
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}
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static void smbus_wait_until_done(void)
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{
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unsigned char byte;
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do {
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byte = inb(SMBUS_IO_HSTSTAT);
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}while((byte &1) == 1);
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while( (byte & ~1) == 0) {
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byte = inb(SMBUS_IO_HSTSTAT);
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}
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}
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int smbus_read_byte(unsigned device, unsigned address)
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{
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unsigned char host_status_register;
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int result;
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smbus_wait_until_ready();
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/* setup transaction */
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/* disable interrupts */
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outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL);
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/* set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_HSTCMD);
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/* set up for a byte data read */
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outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT);
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/* clear the data byte...*/
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outb(0, SMBUS_IO_HSTDAT0);
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/* start the command */
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outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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host_status_register = inb(SMBUS_IO_HSTSTAT);
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/* read results of transaction */
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result = inb(SMBUS_IO_HSTDAT0);
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if (host_status_register != 0x02) {
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result = -1;
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}
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return result;
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}
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#endif /* HAVE_CONSTANT_PROPOGATION */
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#define I440GX_BUS 0
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#define I440GX_DEVFN ((0x00 << 3) + 0)
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void sdram_no_memory(void)
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{
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#if HAVE_STRING_SUPPORT
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print_err("No memory!!\n");
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#endif
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while(1) ;
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}
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static void spd_enable_refresh(void)
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{
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/*
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* Effects: Uses serial presence detect to set the
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* refresh rate in the DRAMC register.
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* see spd_set_dramc for the other values.
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* FIXME: Check for illegal/unsupported ram configurations and abort
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*/
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#if HAVE_STATIC_ARRAY_SUPPORT
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static const unsigned char refresh_rates[] = {
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0x01, /* Normal 15.625 us -> 15.6 us */
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0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */
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0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */
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0x02, /* Extended(2x) 31.3 us -> 31.2 us */
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0x03, /* Extended(4x) 62.5 us -> 62.4 us */
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0x04, /* Extended(8x) 125 us -> 124.8 us */
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};
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#endif
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/* Find the first dimm and assume the rest are the same */
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int status;
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int byte;
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unsigned device;
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unsigned refresh_rate;
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byte = -1;
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status = -1;
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device = SMBUS_MEM_DEVICE_START;
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while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) {
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byte = smbus_read_byte(device, 12);
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device += SMBUS_MEM_DEVICE_INC;
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}
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if (byte < 0) {
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/* We couldn't find anything we must have no memory */
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sdram_no_memory();
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}
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byte &= 0x7f;
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/* Default refresh rate be conservative */
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refresh_rate = 5;
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/* see if the ram refresh is a supported one */
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if (byte < 6) {
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#if HAVE_STATIC_ARRAY_SUPPORT
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refresh_rate = refresh_rates[byte];
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#endif
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}
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byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
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byte &= 0xf8;
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byte |= refresh_rate;
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pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte);
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}
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void sdram_enable_refresh(void)
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{
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spd_enable_refresh();
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}
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