138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* chocodile_mcu board configuration */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/*
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* The console task is too big to include in both RO and RW images. Therefore,
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* if the console task is defined, then only build an RW image. This can be
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* useful for debugging to have a full console. Otherwise, without this task,
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* a full RO and RW is built with a limited one-way output console.
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*/
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#ifdef HAS_TASK_CONSOLE
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/*
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* The flash size is only 32kB.
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* No space for 2 partitions,
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* put only RW at the beginning of the flash
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*/
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#undef CONFIG_FW_INCLUDE_RO
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#undef CONFIG_RW_MEM_OFF
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#define CONFIG_RW_MEM_OFF 0
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#undef CONFIG_RO_SIZE
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#define CONFIG_RO_SIZE 0
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/* Fake full size if we had a RO partition */
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#undef CONFIG_RW_SIZE
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#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
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#endif /* HAS_TASK_CONSOLE */
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/* 48 MHz SYSCLK clock frequency */
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#define CPU_CLOCK 48000000
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/* the UART console is on USART1 (PA9/PA10) */
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#undef CONFIG_UART_CONSOLE
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#define CONFIG_UART_CONSOLE 1
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/* Optional features */
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#define CONFIG_ADC
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#undef CONFIG_ADC_WATCHDOG
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#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY
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#define CONFIG_BOARD_PRE_INIT
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#define CONFIG_COMMON_GPIO_SHORTNAMES
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#undef CONFIG_DEBUG_ASSERT
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#define CONFIG_FORCE_CONSOLE_RESUME
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#define CONFIG_HIBERNATE
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#undef CONFIG_HOSTCMD_EVENTS
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#define CONFIG_HW_CRC
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#undef CONFIG_LID_SWITCH
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#define CONFIG_LOW_POWER_IDLE
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#define CONFIG_LTO
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#define CONFIG_STM_HWTIMER32
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#undef CONFIG_TASK_PROFILING
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#undef CONFIG_UART_TX_BUF_SIZE
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#undef CONFIG_UART_TX_DMA
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#undef CONFIG_UART_RX_DMA
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#define CONFIG_UART_TX_BUF_SIZE 128
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#define CONFIG_USB_PD_PORT_COUNT 1
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#define CONFIG_USB_PD_TCPC
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#define CONFIG_USB_PD_VBUS_DETECT_NONE
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#define CONFIG_USB_PD_TCPM_STUB
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#define CONFIG_USB_SM_FRAMEWORK
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#define CONFIG_USB_TYPEC_CTVPD
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#define CONFIG_USB_PD_DUAL_ROLE
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#define CONFIG_USB_PD_INTERNAL_COMP
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#define CONFIG_VBOOT_HASH
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#define CONFIG_WATCHDOG
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#undef CONFIG_WATCHDOG_HELP
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#define CONFIG_USB_PID 0x5036
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#define VPD_HW_VERSION 0x0001
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#define VPD_FW_VERSION 0x0001
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/* USB bcdDevice */
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#define USB_BCD_DEVICE 0
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/* Vbus impedance in milliohms */
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#define VPD_VBUS_IMPEDANCE 65
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/* GND impedance in milliohms */
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#define VPD_GND_IMPEDANCE 33
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/*
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* TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
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* MP FW.
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*/
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#define CONFIG_SYSTEM_UNLOCKED
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#ifdef HAS_TASK_CONSOLE
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#undef CONFIG_CONSOLE_HISTORY
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#define CONFIG_CONSOLE_HISTORY 2
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#else
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#undef CONFIG_CONSOLE_CMDHELP
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#define CONFIG_DEBUG_PRINTF
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#define UARTN CONFIG_UART_CONSOLE
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#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
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#endif /* HAS_TASK_CONSOLE */
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/* Use PSTATE embedded in the RO image, not in its own erase block */
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#undef CONFIG_FLASH_PSTATE_BANK
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#undef CONFIG_FW_PSTATE_SIZE
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#define CONFIG_FW_PSTATE_SIZE 0
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#ifndef __ASSEMBLER__
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_ADC 3
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#include "gpio_signal.h"
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/* ADC signal */
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enum adc_channel {
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ADC_VCONN_VSENSE = 0,
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ADC_CC_VPDMCU,
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ADC_CC_RP3A0_RD_L,
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ADC_RDCONNECT_REF,
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ADC_CC1_RP3A0_RD_L,
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ADC_CC2_RP3A0_RD_L,
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ADC_HOST_VBUS_VSENSE,
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ADC_CHARGE_VBUS_VSENSE,
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ADC_CC1_RPUSB_ODH,
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ADC_CC2_RPUSB_ODH,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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/* 1.5A Rp */
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#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
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#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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