184 lines
5.1 KiB
C
184 lines
5.1 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hatch Fingerprint MCU configuration */
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#ifndef __BOARD_H
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#define __BOARD_H
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#define CONFIG_SYSTEM_UNLOCKED
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/*
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* Flash layout: we redefine the sections offsets and sizes as we want to
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* include a rollback region, and will use RO/RW regions of different sizes.
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*/
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#undef _IMAGE_SIZE
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#undef CONFIG_ROLLBACK_OFF
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#undef CONFIG_ROLLBACK_SIZE
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#undef CONFIG_FLASH_PSTATE
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#undef CONFIG_FW_PSTATE_SIZE
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#undef CONFIG_FW_PSTATE_OFF
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#undef CONFIG_SHAREDLIB_SIZE
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#undef CONFIG_RO_MEM_OFF
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#undef CONFIG_RO_STORAGE_OFF
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#undef CONFIG_RO_SIZE
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#undef CONFIG_RW_MEM_OFF
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#undef CONFIG_RW_STORAGE_OFF
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#undef CONFIG_RW_SIZE
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#undef CONFIG_EC_PROTECTED_STORAGE_OFF
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#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
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#undef CONFIG_EC_WRITABLE_STORAGE_OFF
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#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
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#undef CONFIG_WP_STORAGE_OFF
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#undef CONFIG_WP_STORAGE_SIZE
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#undef CONFIG_RAM_SIZE
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#define CONFIG_RAM_SIZE 0x40000 /* 256 KB */
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#undef CONFIG_FLASH_SIZE
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#define CONFIG_FLASH_SIZE (1 * 1024 * 1024)
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#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
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#define CONFIG_SHAREDLIB_SIZE 0
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_STORAGE_OFF 0
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#define CONFIG_RO_SIZE (128 * 1024)
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/* EC rollback protection block */
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#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
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#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
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#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
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#define CONFIG_RW_STORAGE_OFF 0
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#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \
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(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
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#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
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#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/*
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* We want to prevent flash readout, and use it as indicator of protection
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* status.
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*/
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#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
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/* the UART console is on USART1 */
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#undef CONFIG_UART_CONSOLE
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#define CONFIG_UART_CONSOLE 1
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#define CONFIG_UART_TX_DMA
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#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART1_TX
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 2048
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#undef CONFIG_UART_TX_DMA
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#undef CONFIG_UART_RX_DMA
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#define CONFIG_UART_TX_REQ_CH 4
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#define CONFIG_UART_RX_REQ_CH 4
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/* Optional features */
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#undef CONFIG_ADC
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#define CONFIG_CMD_IDLE_STATS
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#define CONFIG_DMA
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/*FIXME*/
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/*#define CONFIG_FORCE_CONSOLE_RESUME*/
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#define CONFIG_FPU
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#undef CONFIG_HIBERNATE
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#define CONFIG_HOST_COMMAND_STATUS
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#undef CONFIG_I2C
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#undef CONFIG_LID_SWITCH
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/*FIXME*/
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/*#define CONFIG_LOW_POWER_IDLE*/
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#define CONFIG_MKBP_EVENT
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#define CONFIG_MKBP_USE_GPIO
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#define CONFIG_PRINTF_LEGACY_LI_FORMAT
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#define CONFIG_SHA256
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#define CONFIG_SHA256_UNROLLED
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#define CONFIG_SPI
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#define CONFIG_STM_HWTIMER32
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#define CONFIG_SUPPRESSED_HOST_COMMANDS \
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EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
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#undef CONFIG_TASK_PROFILING
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#define CONFIG_WATCHDOG_HELP
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#define CONFIG_WP_ACTIVE_HIGH
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/* SPI configuration for the fingerprint sensor */
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#define CONFIG_SPI_MASTER
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#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */
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#ifdef SECTION_IS_RW
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#define CONFIG_FP_SENSOR_FPC1025
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/* TODO(b/130249462): remove for release */
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#define CONFIG_CMD_FPSENSOR_DEBUG
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/*
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* Use the malloc code only in the RW section (for the private library),
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* we cannot enable it in RO since it is not compatible with the RW verification
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* (shared_mem_init done too late).
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*/
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#define CONFIG_MALLOC
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/*
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* FP buffers are allocated in regular SRAM on STM32F4.
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* TODO(b/124773209): Instead of defining to empty, #undef once all CLs that
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* depend on FP_*_SECTION have landed. Also rename the variables to CONFIG_*.
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*/
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#define FP_FRAME_SECTION
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#define FP_TEMPLATE_SECTION
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#else /* SECTION_IS_RO */
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/* RO verifies the RW partition signature */
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#define CONFIG_RSA
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#define CONFIG_RSA_KEY_SIZE 3072
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#define CONFIG_RSA_EXPONENT_3
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#define CONFIG_RWSIG
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#endif
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#define CONFIG_RWSIG_TYPE_RWSIG
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/* RW does slow compute, RO does slow flash erase. */
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#undef CONFIG_WATCHDOG_PERIOD_MS
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#define CONFIG_WATCHDOG_PERIOD_MS 10000
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/*
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* Add rollback protection
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*/
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#define CONFIG_ROLLBACK
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#define CONFIG_ROLLBACK_SECRET_SIZE 32
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#define CONFIG_MPU
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#define CONFIG_ROLLBACK_MPU_PROTECT
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/*
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* We do not use any "locally" generated entropy: this is normally used
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* to add local entropy when the main source of entropy is remote.
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*/
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#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
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#ifdef SECTION_IS_RW
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#undef CONFIG_ROLLBACK_UPDATE
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#endif
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#define CONFIG_AES
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#define CONFIG_AES_GCM
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#define CONFIG_RNG
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SPI_XFER
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#ifndef __ASSEMBLER__
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_WATCHDOG 16
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#include "gpio_signal.h"
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void fps_event(enum gpio_signal signal);
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#endif /* !__ASSEMBLER__ */
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#endif /* __BOARD_H */
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