650 lines
17 KiB
C
650 lines
17 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Servo micro board configuration */
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#include "common.h"
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#include "console.h"
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#include "ec_version.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "i2c.h"
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#include "queue_policies.h"
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#include "registers.h"
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#include "spi.h"
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#include "task.h"
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#include "timer.h"
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#include "update_fw.h"
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#include "usart-stm32f0.h"
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#include "usart_tx_dma.h"
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#include "usart_rx_dma.h"
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#include "usb_hw.h"
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#include "usb_i2c.h"
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#include "usb_spi.h"
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#include "usb-stream.h"
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#include "util.h"
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#include "gpio_list.h"
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void board_config_pre_init(void)
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{
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/* enable SYSCFG clock */
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STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
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/*
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* the DMA mapping is :
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* Chan 3 : USART3_RX
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* Chan 5 : USART2_RX
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* Chan 6 : USART4_RX (Disable)
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* Chan 6 : SPI2_RX
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* Chan 7 : SPI2_TX
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*
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* i2c : no dma
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* tim16/17: no dma
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*/
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STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
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/* Remap SPI2 to DMA channels 6 and 7 */
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/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
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/* but cros_ec hardcodes a 6/7 assumption in registers.h */
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STM32_SYSCFG_CFGR1 |= BIT(24);
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}
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/******************************************************************************
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* Forward UARTs as a USB serial interface.
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*/
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#define USB_STREAM_RX_SIZE 32
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#define USB_STREAM_TX_SIZE 64
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/******************************************************************************
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* Forward USART2 (EC) as a simple USB serial interface.
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*/
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static struct usart_config const usart2;
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struct usb_stream_config const usart2_usb;
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static struct queue const usart2_to_usb = QUEUE_DIRECT(128, uint8_t,
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usart2.producer, usart2_usb.consumer);
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static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t,
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usart2_usb.producer, usart2.consumer);
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static struct usart_rx_dma const usart2_rx_dma =
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USART_RX_DMA(STM32_DMAC_CH5, 32);
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static struct usart_config const usart2 =
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USART_CONFIG(usart2_hw,
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usart2_rx_dma.usart_rx,
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usart_tx_interrupt,
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115200,
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0,
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usart2_to_usb,
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usb_to_usart2);
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USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
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USB_IFACE_USART2_STREAM,
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USB_STR_USART2_STREAM_NAME,
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USB_EP_USART2_STREAM,
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USB_STREAM_RX_SIZE,
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USB_STREAM_TX_SIZE,
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usb_to_usart2,
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usart2_to_usb,
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usart2)
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/******************************************************************************
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* Forward USART3 (CPU) as a simple USB serial interface.
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*/
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static struct usart_config const usart3;
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struct usb_stream_config const usart3_usb;
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static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
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usart3.producer, usart3_usb.consumer);
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static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
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usart3_usb.producer, usart3.consumer);
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static struct usart_rx_dma const usart3_rx_dma =
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USART_RX_DMA(STM32_DMAC_CH3, 32);
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static struct usart_config const usart3 =
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USART_CONFIG(usart3_hw,
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usart3_rx_dma.usart_rx,
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usart_tx_interrupt,
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115200,
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0,
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usart3_to_usb,
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usb_to_usart3);
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USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
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USB_IFACE_USART3_STREAM,
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USB_STR_USART3_STREAM_NAME,
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USB_EP_USART3_STREAM,
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USB_STREAM_RX_SIZE,
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USB_STREAM_TX_SIZE,
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usb_to_usart3,
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usart3_to_usb,
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usart3)
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/******************************************************************************
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* Forward USART4 (cr50) as a simple USB serial interface.
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* We cannot enable DMA due to lack of DMA channels.
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*/
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static struct usart_config const usart4;
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struct usb_stream_config const usart4_usb;
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static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
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usart4.producer, usart4_usb.consumer);
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static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
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usart4_usb.producer, usart4.consumer);
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static struct usart_config const usart4 =
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USART_CONFIG(usart4_hw,
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usart_rx_interrupt,
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usart_tx_interrupt,
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115200,
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0,
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usart4_to_usb,
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usb_to_usart4);
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USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
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USB_IFACE_USART4_STREAM,
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USB_STR_USART4_STREAM_NAME,
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USB_EP_USART4_STREAM,
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USB_STREAM_RX_SIZE,
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USB_STREAM_TX_SIZE,
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usb_to_usart4,
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usart4_to_usb,
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usart4)
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/******************************************************************************
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* Check parity setting on usarts.
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*/
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static int command_uart_parity(int argc, char **argv)
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{
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int parity = 0, newparity;
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struct usart_config const *usart;
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char *e;
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if ((argc < 2) || (argc > 3))
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return EC_ERROR_PARAM_COUNT;
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if (!strcasecmp(argv[1], "usart2"))
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usart = &usart2;
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else if (!strcasecmp(argv[1], "usart3"))
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usart = &usart3;
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else if (!strcasecmp(argv[1], "usart4"))
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usart = &usart4;
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else
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return EC_ERROR_PARAM1;
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if (argc == 3) {
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parity = strtoi(argv[2], &e, 0);
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if (*e || (parity < 0) || (parity > 2))
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return EC_ERROR_PARAM2;
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usart_set_parity(usart, parity);
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}
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newparity = usart_get_parity(usart);
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ccprintf("Parity on %s is %d.\n", argv[1], newparity);
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if ((argc == 3) && (newparity != parity))
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return EC_ERROR_UNKNOWN;
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
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"usart[2|3|4] [0|1|2]",
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"Set parity on uart");
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/******************************************************************************
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* Set baud rate setting on usarts.
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*/
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static int command_uart_baud(int argc, char **argv)
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{
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int baud = 0;
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struct usart_config const *usart;
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char *e;
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if ((argc < 2) || (argc > 3))
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return EC_ERROR_PARAM_COUNT;
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if (!strcasecmp(argv[1], "usart2"))
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usart = &usart2;
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else if (!strcasecmp(argv[1], "usart3"))
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usart = &usart3;
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else if (!strcasecmp(argv[1], "usart4"))
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usart = &usart4;
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else
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return EC_ERROR_PARAM1;
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baud = strtoi(argv[2], &e, 0);
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if (*e || baud < 0)
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return EC_ERROR_PARAM2;
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usart_set_baud(usart, baud);
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
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"usart[2|3|4] rate",
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"Set baud rate on uart");
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/******************************************************************************
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* Commands for sending the magic non-I2C handshake over I2C bus wires to an
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* ITE IT8320 EC chip to enable direct firmware update (DFU) over I2C mode.
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*/
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#define KHz 1000
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#define MHz (1000 * KHz)
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/*
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* These constants are values that one might want to try changing if
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* enable_ite_dfu stops working, or does not work on a new ITE EC chip revision.
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*/
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#define ITE_DFU_I2C_CMD_ADDR_FLAGS 0x5A
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#define ITE_DFU_I2C_DATA_ADDR_FLAGS 0x35
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#define SMCLK_WAVEFORM_PERIOD_HZ (100 * KHz)
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#define SMDAT_WAVEFORM_PERIOD_HZ (200 * KHz)
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#define START_DELAY_MS 5
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#define SPECIAL_WAVEFORM_MS 50
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#define PLL_STABLE_MS 10
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/*
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* Digital line levels to hold before (PRE_) or after (POST_) sending the
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* special waveforms. 0 for low, 1 for high.
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*/
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#define SMCLK_PRE_LEVEL 0
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#define SMDAT_PRE_LEVEL 0
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#define SMCLK_POST_LEVEL 0
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#define SMDAT_POST_LEVEL 0
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/* The caller should hold the i2c_lock() for I2C_PORT_MASTER. */
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static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output)
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{
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/*
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* Ideally the write and read would be done in one I2C transaction, as
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* is normally done when reading from the same I2C address that the
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* write was sent to. The ITE EC is abnormal in that regard, with its
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* different addresses for writes vs reads.
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*
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* i2c_xfer() does not support that. Its I2C_XFER_START and
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* I2C_XFER_STOP flag bits do not cleanly support that scenario, they
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* are for continuing transfers without either of STOP or START
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* in-between.
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*
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* For what it's worth, the iteflash.c FTDI-based implementation of this
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* does the same thing, issuing a STOP between the write and read. This
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* works, even if perhaps it should not.
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*/
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int ret;
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/* Tell the ITE EC which register we want to read. */
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ret = i2c_xfer_unlocked(I2C_PORT_MASTER,
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ITE_DFU_I2C_CMD_ADDR_FLAGS,
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®ister_offset, sizeof(register_offset),
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NULL, 0, I2C_XFER_SINGLE);
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if (ret != EC_SUCCESS)
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return ret;
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/* Read in the 1 byte register value. */
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ret = i2c_xfer_unlocked(I2C_PORT_MASTER,
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ITE_DFU_I2C_DATA_ADDR_FLAGS,
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NULL, 0,
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output, sizeof(*output), I2C_XFER_SINGLE);
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return ret;
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}
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/* Helper function to read ITE chip ID, for verifying ITE DFU mode. */
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static int cprint_ite_chip_id(void)
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{
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/*
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* Per i2c_read8() implementation, use an array even for single byte
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* reads to ensure alignment for DMA on STM32.
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*/
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uint8_t chipid1[1];
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uint8_t chipid2[1];
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uint8_t chipver[1];
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int ret;
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int chip_version;
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int flash_kb;
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i2c_lock(I2C_PORT_MASTER, 1);
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/* Read the CHIPID1 register. */
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ret = ite_i2c_read_register(0x00, chipid1);
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if (ret != EC_SUCCESS)
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goto unlock;
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/* Read the CHIPID2 register. */
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ret = ite_i2c_read_register(0x01, chipid2);
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if (ret != EC_SUCCESS)
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goto unlock;
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/* Read the CHIPVER register. */
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ret = ite_i2c_read_register(0x02, chipver);
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unlock:
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i2c_lock(I2C_PORT_MASTER, 0);
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if (ret != EC_SUCCESS)
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return ret;
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/*
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* Compute chip version and embedded flash size from the CHIPVER value.
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*
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* Chip version is mapping from bit 3-0
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* Flash size is mapping from bit 7-4
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*
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* Chip Version (bits 3-0)
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* 0: AX
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* 1: BX
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* 2: CX
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* 3: DX
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*
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* CX or prior flash size (bits 7-4)
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* 0:128KB
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* 4:192KB
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* 8:256KB
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*
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* DX flash size (bits 7-4)
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* 0:128KB
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* 2:192KB
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* 4:256KB
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* 6:384KB
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* 8:512KB
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*/
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chip_version = chipver[0] & 0x07;
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if (chip_version < 0x3) {
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/* Chip version is CX or earlier. */
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switch (chipver[0] >> 4) {
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case 0:
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flash_kb = 128;
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break;
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case 4:
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flash_kb = 192;
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break;
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case 8:
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flash_kb = 256;
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break;
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default:
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flash_kb = -2;
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}
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} else if (chip_version == 0x3) {
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/* Chip version is DX. */
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switch (chipver[0] >> 4) {
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case 0:
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flash_kb = 128;
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break;
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case 2:
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flash_kb = 192;
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break;
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case 4:
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flash_kb = 256;
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break;
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case 6:
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flash_kb = 384;
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break;
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case 8:
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flash_kb = 512;
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break;
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default:
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flash_kb = -3;
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}
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} else {
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/* Unrecognized chip version. */
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flash_kb = -1;
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}
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ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ",
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chipid1[0], chipid2[0], chipver[0]);
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ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10);
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/*
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* IT8320_eflash_SMBus_Programming_Guide.pdf says it is an error if
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* CHIPID1 != 0x83.
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*/
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if (chipid1[0] != 0x83)
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ret = EC_ERROR_HW_INTERNAL;
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return ret;
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}
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/* Enable ITE direct firmware update (DFU) mode. */
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static int command_enable_ite_dfu(int argc, char **argv)
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{
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if (argc > 1)
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return EC_ERROR_PARAM_COUNT;
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/* Enable peripheral clocks. */
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STM32_RCC_APB2ENR |=
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STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN;
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/* Reset timer registers which are not otherwise set below. */
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STM32_TIM_CR2(16) = 0x0000;
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STM32_TIM_CR2(17) = 0x0000;
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STM32_TIM_DIER(16) = 0x0000;
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STM32_TIM_DIER(17) = 0x0000;
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STM32_TIM_SR(16) = 0x0000;
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STM32_TIM_SR(17) = 0x0000;
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STM32_TIM_CNT(16) = 0x0000;
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STM32_TIM_CNT(17) = 0x0000;
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STM32_TIM_RCR(16) = 0x0000;
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STM32_TIM_RCR(17) = 0x0000;
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STM32_TIM_DCR(16) = 0x0000;
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STM32_TIM_DCR(17) = 0x0000;
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STM32_TIM_DMAR(16) = 0x0000;
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STM32_TIM_DMAR(17) = 0x0000;
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/* Prescale to 1 MHz and use ARR to achieve NNN KHz periods. */
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/* This approach is seen in STM's documentation. */
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STM32_TIM_PSC(16) = (CPU_CLOCK / MHz) - 1;
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STM32_TIM_PSC(17) = (CPU_CLOCK / MHz) - 1;
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/* Set the waveform periods based on 1 MHz prescale. */
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STM32_TIM_ARR(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) - 1;
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STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1;
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/* Set output compare 1 mode to PWM mode 1 and enable preload. */
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STM32_TIM_CCMR1(16) =
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STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
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STM32_TIM_CCMR1(17) =
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STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
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/* Enable output compare 1. */
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STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1E;
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STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E;
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/* Enable main output. */
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STM32_TIM_BDTR(16) = STM32_TIM_BDTR_MOE;
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STM32_TIM_BDTR(17) = STM32_TIM_BDTR_MOE;
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/* Update generation (reinitialize counters). */
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STM32_TIM_EGR(16) = STM32_TIM_EGR_UG;
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STM32_TIM_EGR(17) = STM32_TIM_EGR_UG;
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/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
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STM32_TIM_CCR1(16) = SMCLK_PRE_LEVEL ? 0xFFFF : 0x0000;
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STM32_TIM_CCR1(17) = SMDAT_PRE_LEVEL ? 0xFFFF : 0x0000;
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/* Enable timer counters. */
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STM32_TIM_CR1(16) = STM32_TIM_CR1_CEN;
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STM32_TIM_CR1(17) = STM32_TIM_CR1_CEN;
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/* Set PB8 GPIO to alternate mode TIM16_CH1. */
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/* Set PB9 GPIO to alternate mode TIM17_CH1. */
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gpio_config_module(MODULE_I2C_TIMERS, 1);
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msleep(START_DELAY_MS);
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/* Set pulse width to half of waveform period. */
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STM32_TIM_CCR1(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) / 2;
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STM32_TIM_CCR1(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) / 2;
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msleep(SPECIAL_WAVEFORM_MS);
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/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
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STM32_TIM_CCR1(16) = SMCLK_POST_LEVEL ? 0xFFFF : 0x0000;
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STM32_TIM_CCR1(17) = SMDAT_POST_LEVEL ? 0xFFFF : 0x0000;
|
|
|
|
msleep(PLL_STABLE_MS);
|
|
|
|
/* Set PB8 GPIO to alternate mode I2C1_SCL. */
|
|
/* Set PB9 GPIO to alternate mode I2C1_DAT. */
|
|
gpio_config_module(MODULE_I2C, 1);
|
|
|
|
/* Disable timer counters. */
|
|
STM32_TIM_CR1(16) = 0x0000;
|
|
STM32_TIM_CR1(17) = 0x0000;
|
|
|
|
/* Disable peripheral clocks. */
|
|
STM32_RCC_APB2ENR &=
|
|
~(STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN);
|
|
|
|
return cprint_ite_chip_id();
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(
|
|
enable_ite_dfu, command_enable_ite_dfu, "",
|
|
"Enable ITE Direct Firmware Update (DFU) mode");
|
|
|
|
/* Read ITE chip ID. Can be used to verify ITE DFU mode. */
|
|
/*
|
|
* TODO(b/79684405): There is nothing specific about Servo Micro in the
|
|
* implementation of the "get_ite_chipid" command. Move the implementation to a
|
|
* common place so that it need not be reimplemented for every Servo version
|
|
* that "enable_ite_dfu" is implemented for.
|
|
*/
|
|
static int command_get_ite_chipid(int argc, char **argv)
|
|
{
|
|
if (argc > 1)
|
|
return EC_ERROR_PARAM_COUNT;
|
|
|
|
return cprint_ite_chip_id();
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(
|
|
get_ite_chipid, command_get_ite_chipid, "",
|
|
"Read ITE EC chip ID, version, flash size (must be in DFU mode)");
|
|
|
|
/******************************************************************************
|
|
* Define the strings used in our USB descriptors.
|
|
*/
|
|
const void *const usb_strings[] = {
|
|
[USB_STR_DESC] = usb_string_desc,
|
|
[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
|
|
[USB_STR_PRODUCT] = USB_STRING_DESC("Servo Micro"),
|
|
[USB_STR_SERIALNO] = 0,
|
|
[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
|
|
[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
|
|
[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART3"),
|
|
[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo Shell"),
|
|
[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"),
|
|
[USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("EC"),
|
|
[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
|
|
};
|
|
|
|
BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
|
|
|
|
/******************************************************************************
|
|
* Support SPI bridging over USB, this requires usb_spi_board_enable and
|
|
* usb_spi_board_disable to be defined to enable and disable the SPI bridge.
|
|
*/
|
|
|
|
/* SPI devices */
|
|
const struct spi_device_t spi_devices[] = {
|
|
{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS},
|
|
};
|
|
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
|
|
|
|
void usb_spi_board_enable(struct usb_spi_config const *config)
|
|
{
|
|
/* Configure SPI GPIOs */
|
|
gpio_config_module(MODULE_SPI_FLASH, 1);
|
|
|
|
/* Set all four SPI pins to high speed */
|
|
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
|
|
|
|
/* Enable clocks to SPI2 module */
|
|
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
|
|
|
|
/* Reset SPI2 */
|
|
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
|
|
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
|
|
|
|
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
|
|
}
|
|
|
|
void usb_spi_board_disable(struct usb_spi_config const *config)
|
|
{
|
|
spi_enable(CONFIG_SPI_FLASH_PORT, 0);
|
|
|
|
/* Disable clocks to SPI2 module */
|
|
STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
|
|
|
|
/* Release SPI GPIOs */
|
|
gpio_config_module(MODULE_SPI_FLASH, 0);
|
|
}
|
|
|
|
USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI);
|
|
|
|
/******************************************************************************
|
|
* Support I2C bridging over USB.
|
|
*/
|
|
|
|
/* I2C ports */
|
|
const struct i2c_port_t i2c_ports[] = {
|
|
{"master", I2C_PORT_MASTER, 100,
|
|
GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
|
|
};
|
|
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
|
|
|
|
int usb_i2c_board_is_enabled(void) { return 1; }
|
|
|
|
/******************************************************************************
|
|
* Initialize board.
|
|
*/
|
|
static void board_init(void)
|
|
{
|
|
/* USB to serial queues */
|
|
queue_init(&usart2_to_usb);
|
|
queue_init(&usb_to_usart2);
|
|
queue_init(&usart3_to_usb);
|
|
queue_init(&usb_to_usart3);
|
|
queue_init(&usart4_to_usb);
|
|
queue_init(&usb_to_usart4);
|
|
|
|
/* UART init */
|
|
usart_init(&usart2);
|
|
usart_init(&usart3);
|
|
usart_init(&usart4);
|
|
|
|
/* Enable GPIO expander. */
|
|
gpio_set_level(GPIO_TCA6416_RESET_L, 1);
|
|
|
|
/* Structured enpoints */
|
|
usb_spi_enable(&usb_spi, 1);
|
|
|
|
/* Enable UARTs by default. */
|
|
gpio_set_level(GPIO_UART1_EN_L, 0);
|
|
gpio_set_level(GPIO_UART2_EN_L, 0);
|
|
/* Disable power output. */
|
|
gpio_set_level(GPIO_SPI1_VREF_18, 0);
|
|
gpio_set_level(GPIO_SPI1_VREF_33, 0);
|
|
gpio_set_level(GPIO_SPI2_VREF_18, 0);
|
|
gpio_set_level(GPIO_SPI2_VREF_33, 0);
|
|
/* Enable UART3 routing. */
|
|
gpio_set_level(GPIO_SPI1_MUX_SEL, 1);
|
|
gpio_set_level(GPIO_SPI1_BUF_EN_L, 1);
|
|
gpio_set_level(GPIO_JTAG_BUFIN_EN_L, 0);
|
|
gpio_set_level(GPIO_SERVO_JTAG_TDO_BUFFER_EN, 1);
|
|
gpio_set_level(GPIO_SERVO_JTAG_TDO_SEL, 1);
|
|
gpio_set_flags(GPIO_UART3_RX_JTAG_BUFFER_TO_SERVO_TDO, GPIO_ALTERNATE);
|
|
gpio_set_flags(GPIO_UART3_TX_SERVO_JTAG_TCK, GPIO_ALTERNATE);
|
|
}
|
|
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
|