190 lines
4.9 KiB
C
190 lines
4.9 KiB
C
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* ISH Firmware status register contains currnet ISH FW status.
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* Communication protocol for Host(x64), CSME, and PMC uses this register.
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*/
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#ifndef __ISH_FWST_H
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#define __ISH_FWST_H
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#include "common.h"
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#include "registers.h"
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/*
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* IPC link is up(ready)
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* IPC can be used by other protocols
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*/
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#define IPC_ISH_FWSTS_ILUP_FIELD 0x01
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#define IPC_ISH_FWSTS_ILUP_SHIFT 0
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#define IPC_ISH_FWSTS_ILUP_MASK \
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(IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
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/*
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* HECI layer is up(ready)
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*/
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#define IPC_ISH_FWSTS_HUP_FIELD 0x01
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#define IPC_ISH_FWSTS_HUP_SHIFT 1
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#define IPC_ISH_FWSTS_HUP_MASK \
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(IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
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/*
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* ISH FW reason reason
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*/
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#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F
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#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2
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#define IPC_ISH_FWSTS_FAIL_REASON_MASK \
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(IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
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/*
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* ISH FW reset ID
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*/
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#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F
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#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8
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#define IPC_ISH_FWSTS_RESET_ID_MASK \
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(IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
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/*
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* ISH FW status type
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*/
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enum {
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FWSTS_AFTER_RESET = 0,
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FWSTS_WAIT_FOR_HOST = 4,
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FWSTS_START_KERNEL_DMA = 5,
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FWSTS_FW_IS_RUNNING = 7,
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FWSTS_SENSOR_APP_LOADED = 8,
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FWSTS_SENSOR_APP_RUNNING = 15
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};
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/*
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* General ISH FW status
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*/
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#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F
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#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12
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#define IPC_ISH_FWSTS_FW_STATUS_MASK \
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(IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
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#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01
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#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16
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#define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \
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(IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
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#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01
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#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17
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#define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \
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(IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
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#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01
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#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18
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#define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \
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(IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
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#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01
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#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19
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#define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \
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(IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
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#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F
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#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20
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#define IPC_ISH_FWSTS_POWER_STATE_MASK \
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(IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
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#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07
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#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24
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#define IPC_ISH_FWSTS_AON_CHECK_MASK \
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(IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
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/* get ISH FW status register */
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static inline uint32_t ish_fwst_get(void)
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{
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return IPC_ISH_FWSTS;
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}
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/* set IPC link up */
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static inline void ish_fwst_set_ilup(void)
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{
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IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
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}
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/* clear IPC link up */
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static inline void ish_fwst_clear_ilup(void)
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{
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IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_ILUP_MASK;
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}
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/* return IPC link up state */
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static inline int ish_fwst_is_ilup_set(void)
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{
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return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_ILUP_MASK);
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}
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/* set HECI up */
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static inline void ish_fwst_set_hup(void)
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{
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IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
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}
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/* clear HECI up */
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static inline void ish_fwst_clear_hup(void)
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{
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IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_HUP_MASK;
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}
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/* get HECI up status */
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static inline int ish_fwst_is_hup_set(void)
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{
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return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_HUP_MASK);
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}
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/* set fw failure reason */
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static inline void ish_fwst_set_fail_reason(uint32_t val)
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{
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uint32_t fwst = IPC_ISH_FWSTS;
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IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
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(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
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}
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/* get fw failure reason */
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static inline uint32_t ish_fwst_get_fail_reason(void)
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{
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return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK)
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>> IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
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}
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/* set reset id */
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static inline void ish_fwst_set_reset_id(uint32_t val)
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{
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uint32_t fwst = IPC_ISH_FWSTS;
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IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
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(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
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}
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/* get reset id */
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static inline uint32_t ish_fwst_get_reset_id(void)
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{
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return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK)
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>> IPC_ISH_FWSTS_RESET_ID_SHIFT;
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}
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/* set general fw status */
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static inline void ish_fwst_set_fw_status(uint32_t val)
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{
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uint32_t fwst = IPC_ISH_FWSTS;
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IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
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(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
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}
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/* get general fw status */
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static inline uint32_t ish_fwst_get_fw_status(void)
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{
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return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK)
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>> IPC_ISH_FWSTS_FW_STATUS_SHIFT;
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}
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#endif /* __ISH_FWST_H */
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