83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_POWER_MGT_H
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#define __CROS_EC_POWER_MGT_H
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#include "common.h"
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#include "registers.h"
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/* power states for ISH */
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enum ish_pm_state {
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/* D0 state: active mode */
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ISH_PM_STATE_D0 = 0,
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/* sleep state: cpu halt */
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ISH_PM_STATE_D0I0,
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/* deep sleep state 1: Trunk Clock Gating(TCG), cpu halt*/
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ISH_PM_STATE_D0I1,
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/* deep sleep state 2: TCG, SRAM retention, cpu halt */
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ISH_PM_STATE_D0I2,
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/* deep sleep state 3: TCG, SRAM power off, cpu halt*/
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ISH_PM_STATE_D0I3,
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/**
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* D3 state: power off state, on ISH5.0, can't do real power off,
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* similar to D0I3, but will reset ISH
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*/
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ISH_PM_STATE_D3,
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/**
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* reset ISH, main FW received 'reboot' command
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*/
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ISH_PM_STATE_RESET,
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/**
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* reset ISH, main FW received reset_prep interrupt during
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* S0->Sx transition.
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*/
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ISH_PM_STATE_RESET_PREP,
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ISH_PM_STATE_NUM
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};
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/* halt ISH minute-ia cpu core */
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static inline void ish_mia_halt(void)
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{
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/* make sure interrupts are enabled before halting */
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__asm__ volatile("sti;\n"
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"hlt;");
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}
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/* reset ISH mintue-ia cpu core */
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__attribute__((noreturn))
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static inline void ish_mia_reset(void)
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{
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/**
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* ISH HW looks at the rising edge of this bit to
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* trigger a MIA reset.
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*/
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ISH_RST_REG = 0;
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ISH_RST_REG = 1;
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__builtin_unreachable();
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}
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/* Initialize power management module. */
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#ifdef CONFIG_LOW_POWER_IDLE
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void ish_pm_init(void);
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#else
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__maybe_unused static void ish_pm_init(void)
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{
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}
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#endif
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/**
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* reset ISH (reset minute-ia cpu core, and power off main SRAM)
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*/
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void ish_pm_reset(enum ish_pm_state pm_state) __attribute__((noreturn));
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/**
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* notify the power management module that the UART for the console is in use.
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*/
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void ish_pm_refresh_console_in_use(void);
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#endif /* __CROS_EC_POWER_MGT_H */
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