617 lines
17 KiB
C
617 lines
17 KiB
C
/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "adc_chip.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "hwtimer.h"
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#include "hwtimer_chip.h"
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#include "intc.h"
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#include "irq_chip.h"
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#include "it83xx_pd.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "util.h"
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/* Console output macros. */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#ifdef CONFIG_LOW_POWER_IDLE
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#define SLEEP_SET_HTIMER_DELAY_USEC 250
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#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2)
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#ifdef CONFIG_ADC
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BUILD_ASSERT(ADC_TIMEOUT_US < SLEEP_SET_HTIMER_DELAY_USEC);
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#endif
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static timestamp_t sleep_mode_t0;
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static timestamp_t sleep_mode_t1;
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static int idle_doze_cnt;
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static int idle_sleep_cnt;
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static uint64_t total_idle_sleep_time_us;
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static uint32_t ec_sleep;
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/*
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* Fixed amount of time to keep the console in use flag true after boot in
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* order to give a permanent window in which the heavy sleep mode is not used.
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*/
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#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
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static int console_in_use_timeout_sec = 5;
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static timestamp_t console_expire_time;
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/* clock source is 32.768KHz */
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#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768)
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#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1)
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#endif /*CONFIG_LOW_POWER_IDLE */
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static int freq;
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struct clock_gate_ctrl {
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volatile uint8_t *reg;
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uint8_t mask;
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};
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static void clock_module_disable(void)
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{
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/* bit0: FSPI interface tri-state */
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IT83XX_SMFI_FLHCTRL3R |= BIT(0);
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/* bit7: USB pad power-on disable */
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IT83XX_GCTRL_PMER2 &= ~BIT(7);
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/* bit7: USB debug disable */
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IT83XX_GCTRL_MCCR &= ~BIT(7);
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clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
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clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
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CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
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CGC_OFFSET_SMBF), 0, 0);
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clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI |
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CGC_OFFSET_USB), 0, 0);
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}
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enum pll_freq_idx {
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PLL_24_MHZ = 1,
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PLL_48_MHZ = 2,
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PLL_96_MHZ = 4,
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};
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static const uint8_t pll_to_idx[8] = {
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0,
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0,
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PLL_24_MHZ,
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0,
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PLL_48_MHZ,
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0,
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0,
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PLL_96_MHZ
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};
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struct clock_pll_t {
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int pll_freq;
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uint8_t pll_setting;
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uint8_t div_fnd;
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uint8_t div_uart;
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uint8_t div_usb;
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uint8_t div_smb;
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uint8_t div_sspi;
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uint8_t div_ec;
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uint8_t div_jtag;
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uint8_t div_pwm;
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uint8_t div_usbpd;
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};
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const struct clock_pll_t clock_pll_ctrl[] = {
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/*
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* UART: 24MHz
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* SMB: 24MHz
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* EC: 8MHz
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* JTAG: 24MHz
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* USBPD: 8MHz
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* USB: 48MHz(no support if PLL=24MHz)
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* SSPI: 48MHz(24MHz if PLL=24MHz)
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*/
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/* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */
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[PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2},
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#ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
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/* PLL:48MHz, MCU:48MHz, Fnd:48MHz */
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[PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5},
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/* PLL:96MHz, MCU:96MHz, Fnd:48MHz */
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[PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb},
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#else
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/* PLL:48MHz, MCU:48MHz, Fnd:24MHz */
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[PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5},
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/* PLL:96MHz, MCU:96MHz, Fnd:32MHz */
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[PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb},
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#endif
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};
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static uint8_t pll_div_fnd;
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static uint8_t pll_div_ec;
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static uint8_t pll_div_jtag;
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static uint8_t pll_setting;
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void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
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{
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IT83XX_ECPM_PLLCTRL = mode;
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/* for deep doze / sleep mode */
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IT83XX_ECPM_PLLCTRL = mode;
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/*
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* barrier: ensure low power mode setting is taken into control
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* register before standby instruction.
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*/
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data_serialization_barrier();
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}
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void __ram_code clock_pll_changed(void)
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{
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IT83XX_GCTRL_SSCR &= ~BIT(0);
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/*
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* Update PLL settings.
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* Writing data to this register doesn't change the
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* PLL frequency immediately until the status is changed
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* into wakeup from the sleep mode.
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* The following code is intended to make the system
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* enter sleep mode, and set up a HW timer to wakeup EC to
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* complete PLL update.
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*/
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IT83XX_ECPM_PLLFREQR = pll_setting;
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/* Pre-set FND clock frequency = PLL / 3 */
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IT83XX_ECPM_SCDCR0 = (2 << 4);
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/* JTAG and EC */
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IT83XX_ECPM_SCDCR3 = (pll_div_jtag << 4) | pll_div_ec;
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/* EC sleep after standby instruction */
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clock_ec_pll_ctrl(EC_PLL_SLEEP);
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if (IS_ENABLED(CHIP_CORE_NDS32)) {
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/* Global interrupt enable */
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asm volatile ("setgie.e");
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/* EC sleep */
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asm("standby wake_grant");
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/* Global interrupt disable */
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asm volatile ("setgie.d");
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} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
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/* Global interrupt enable */
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asm volatile ("csrsi mstatus, 0x8");
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/* EC sleep */
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asm("wfi");
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/* Global interrupt disable */
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asm volatile ("csrci mstatus, 0x8");
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}
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/* New FND clock frequency */
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IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
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/* EC doze after standby instruction */
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clock_ec_pll_ctrl(EC_PLL_DOZE);
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}
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/* NOTE: Don't use this function in other place. */
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static void clock_set_pll(enum pll_freq_idx idx)
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{
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int pll;
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/* TODO(b/134542199): fix me... Changing PLL failed on it83202/ax */
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if (IS_ENABLED(CHIP_VARIANT_IT83202AX))
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return;
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pll_div_fnd = clock_pll_ctrl[idx].div_fnd;
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pll_div_ec = clock_pll_ctrl[idx].div_ec;
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pll_div_jtag = clock_pll_ctrl[idx].div_jtag;
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pll_setting = clock_pll_ctrl[idx].pll_setting;
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/* Update PLL settings or not */
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if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) ||
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((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
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((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
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/* Enable hw timer to wakeup EC from the sleep mode */
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ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
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1, 1, 5, 1, 0);
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task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
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#ifdef CONFIG_HOSTCMD_ESPI
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/*
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* Workaround for (b:70537592):
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* We have to set chip select pin as input mode in order to
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* change PLL.
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*/
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IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7);
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#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
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/*
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* On DX version, we have to disable eSPI pad before changing
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* PLL sequence or sequence will fail if CS# pin is low.
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*/
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espi_enable_pad(0);
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#endif
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#endif
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/* Update PLL settings. */
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clock_pll_changed();
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#ifdef CONFIG_HOSTCMD_ESPI
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#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
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/* Enable eSPI pad after changing PLL sequence. */
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espi_enable_pad(1);
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#endif
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/* (b:70537592) Change back to ESPI CS# function. */
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IT83XX_GPIO_GPCRM5 &= ~0xc0;
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#endif
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}
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/* Get new/current setting of PLL frequency */
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pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf];
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/* USB and UART */
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IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) |
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clock_pll_ctrl[pll].div_uart;
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/* SSPI and SMB */
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IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) |
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clock_pll_ctrl[pll].div_smb;
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/* USBPD and PWM */
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IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) |
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clock_pll_ctrl[pll].div_pwm;
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/* Current PLL frequency */
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freq = clock_pll_ctrl[pll].pll_freq;
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}
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void clock_init(void)
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{
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uint32_t image_type = (uint32_t)clock_init;
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/* To change interrupt vector base if at RW image */
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if (image_type > CONFIG_RW_MEM_OFF)
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/* Interrupt Vector Table Base Address, in 64k Byte unit */
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IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
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#if (PLL_CLOCK == 24000000) || \
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(PLL_CLOCK == 48000000) || \
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(PLL_CLOCK == 96000000)
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/* Set PLL frequency */
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clock_set_pll(PLL_CLOCK / 24000000);
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#else
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#error "Support only for PLL clock speed of 24/48/96MHz."
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#endif
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/*
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* The VCC power status is treated as power-on.
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* The VCC supply of LPC and related functions (EC2I,
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* KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI).
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* It means VCC (pin 11) should be logic high before using
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* these functions, or firmware treats VCC logic high
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* as following setting.
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*/
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IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
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#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
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/*
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* Because we don't support eSPI HW reset function (b/111480168) on DX
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* version, so we have to reset eSPI configurations during init to
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* ensure Host and EC are synchronized (especially for the field of
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* I/O mode)
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*/
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if (!system_jumped_to_this_image())
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espi_fw_reset_module();
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#endif
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/* Turn off auto clock gating. */
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IT83XX_ECPM_AUTOCG = 0x00;
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/* Default doze mode */
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clock_ec_pll_ctrl(EC_PLL_DOZE);
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clock_module_disable();
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#ifdef CONFIG_HOSTCMD_X86
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IT83XX_WUC_WUESR4 = BIT(2);
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task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
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/* bit2, wake-up enable for LPC access */
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IT83XX_WUC_WUENR4 |= BIT(2);
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#endif
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}
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int clock_get_freq(void)
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{
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return freq;
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}
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/**
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* Enable clock to specified peripheral
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*
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* @param offset Should be element of clock_gate_offsets enum.
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* Bits 8-15 specify the ECPM offset of the specific clock reg.
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* Bits 0-7 specify the mask for the clock register.
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* @param mask Unused
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* @param mode Unused
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*/
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void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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volatile uint8_t *reg = (volatile uint8_t *)
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(IT83XX_ECPM_BASE + (offset >> 8));
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uint8_t reg_mask = offset & 0xff;
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/*
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* Note: CGCTRL3R, bit 6, must always write 1, but since there is no
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* offset argument that addresses this bit, then we are guaranteed
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* that this line will write a 1 to that bit.
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*/
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*reg &= ~reg_mask;
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}
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/**
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* Disable clock to specified peripheral
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*
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* @param offset Should be element of clock_gate_offsets enum.
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* Bits 8-15 specify the ECPM offset of the specific clock reg.
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* Bits 0-7 specify the mask for the clock register.
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* @param mask Unused
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* @param mode Unused
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*/
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void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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volatile uint8_t *reg = (volatile uint8_t *)
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(IT83XX_ECPM_BASE + (offset >> 8));
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uint8_t reg_mask = offset & 0xff;
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uint8_t tmp_mask = 0;
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/* CGCTRL3R, bit 6, must always write a 1. */
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tmp_mask |= ((offset >> 8) == IT83XX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00;
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*reg |= reg_mask | tmp_mask;
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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void clock_refresh_console_in_use(void)
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{
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/* Set console in use expire time. */
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console_expire_time = get_time();
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console_expire_time.val += console_in_use_timeout_sec * SECOND;
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}
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static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
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uint32_t count)
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{
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IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
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IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
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IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count;
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IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3;
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}
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static void clock_htimer_enable(void)
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{
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uint32_t c;
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/* change event timer clock source to 32.768 KHz */
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#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
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c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER));
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#else
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c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
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#endif
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clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c);
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}
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static int clock_allow_low_power_idle(void)
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{
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if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)))
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return 0;
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if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
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et_ctrl_regs[EVENT_EXT_TIMER].mask)
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return 0;
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#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
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if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
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#else
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if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
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#endif
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SLEEP_SET_HTIMER_DELAY_USEC)
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return 0;
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sleep_mode_t0 = get_time();
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if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) ||
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(sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
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return 0;
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if (sleep_mode_t0.val < console_expire_time.val)
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return 0;
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return 1;
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}
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int clock_ec_wake_from_sleep(void)
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{
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return ec_sleep;
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}
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void clock_cpu_standby(void)
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{
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/* standby instruction */
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if (IS_ENABLED(CHIP_CORE_NDS32)) {
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asm("standby wake_grant");
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} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
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/*
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* An interrupt is not able to wake EC up from low power mode.
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* (AX bug)
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*/
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if (IS_ENABLED(CHIP_VARIANT_IT83202AX))
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asm("nop");
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else
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asm("wfi");
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}
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}
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void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
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{
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int i;
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/* disable all interrupts */
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interrupt_disable();
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for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
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chip_disable_irq(i);
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chip_clear_pending_irq(i);
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}
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/* bit5: watchdog is disabled. */
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IT83XX_ETWD_ETWCTRL |= BIT(5);
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/* Setup GPIOs for hibernate */
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if (board_hibernate_late)
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board_hibernate_late();
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if (seconds || microseconds) {
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/* At least 1 ms for hibernate. */
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uint64_t c = (seconds * 1000 + microseconds / 1000 + 1) * 1024;
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uint64divmod(&c, 1000);
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/* enable a 56-bit timer and clock source is 1.024 KHz */
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ext_timer_stop(FREE_EXT_TIMER_L, 1);
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ext_timer_stop(FREE_EXT_TIMER_H, 1);
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IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_L) = EXT_PSR_1P024K_HZ;
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IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_H) = EXT_PSR_1P024K_HZ;
|
|
IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_L) = c & 0xffffff;
|
|
IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = (c >> 24) & 0xffffffff;
|
|
ext_timer_start(FREE_EXT_TIMER_H, 1);
|
|
ext_timer_start(FREE_EXT_TIMER_L, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_USB_PD_TCPM_ITE83XX
|
|
/*
|
|
* Disable integrated pd modules in hibernate for
|
|
* better power consumption.
|
|
*/
|
|
for (i = 0; i < USBPD_PORT_COUNT; i++)
|
|
it83xx_disable_pd_module(i);
|
|
#endif
|
|
|
|
for (i = 0; i < hibernate_wake_pins_used; ++i)
|
|
gpio_enable_interrupt(hibernate_wake_pins[i]);
|
|
|
|
/* EC sleep */
|
|
ec_sleep = 1;
|
|
#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
|
|
defined(CONFIG_HOSTCMD_ESPI)
|
|
/* Disable eSPI pad. */
|
|
espi_enable_pad(0);
|
|
#endif
|
|
clock_ec_pll_ctrl(EC_PLL_SLEEP);
|
|
interrupt_enable();
|
|
/* standby instruction */
|
|
clock_cpu_standby();
|
|
|
|
/* we should never reach that point */
|
|
__builtin_unreachable();
|
|
}
|
|
|
|
void clock_sleep_mode_wakeup_isr(void)
|
|
{
|
|
uint32_t st_us, c;
|
|
|
|
/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
|
|
if (clock_ec_wake_from_sleep()) {
|
|
#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
|
|
defined(CONFIG_HOSTCMD_ESPI)
|
|
/*
|
|
* Enable eSPI pad.
|
|
* We will not need to enable eSPI pad here if Dx is able to
|
|
* enable watchdog hardware reset function. But the function is
|
|
* failed (b:111264984), so the following system reset is
|
|
* software reset (PLL setting is not reset).
|
|
* We will not go into the change PLL sequence on reboot if PLL
|
|
* setting is the same, so the operation of enabling eSPI pad we
|
|
* added in clock_set_pll() will not be applied.
|
|
*/
|
|
espi_enable_pad(1);
|
|
#endif
|
|
system_reset(SYSTEM_RESET_HARD);
|
|
}
|
|
|
|
if (IT83XX_ECPM_PLLCTRL == EC_PLL_DEEP_DOZE) {
|
|
clock_ec_pll_ctrl(EC_PLL_DOZE);
|
|
|
|
/* update free running timer */
|
|
c = 0xffffffff - IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
|
|
st_us = TIMER_32P768K_CNT_TO_US(c);
|
|
sleep_mode_t1.val = sleep_mode_t0.val + st_us;
|
|
__hw_clock_source_set(sleep_mode_t1.le.lo);
|
|
|
|
/* reset event timer and clock source is 8 MHz */
|
|
clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff);
|
|
task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
|
|
process_timers(0);
|
|
#ifdef CONFIG_HOSTCMD_X86
|
|
/* disable lpc access wui */
|
|
task_disable_irq(IT83XX_IRQ_WKINTAD);
|
|
IT83XX_WUC_WUESR4 = BIT(2);
|
|
task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
|
|
#endif
|
|
/* disable uart wui */
|
|
uart_exit_dsleep();
|
|
/* Record time spent in sleep. */
|
|
total_idle_sleep_time_us += st_us;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Low power idle task. Executed when no tasks are ready to be scheduled.
|
|
*/
|
|
void __idle(void)
|
|
{
|
|
console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
|
|
/* init hw timer and clock source is 32.768 KHz */
|
|
ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0,
|
|
0xffffffff, 1, 1);
|
|
|
|
/*
|
|
* Print when the idle task starts. This is the lowest priority task,
|
|
* so this only starts once all other tasks have gotten a chance to do
|
|
* their task inits and have gone to sleep.
|
|
*/
|
|
CPRINTS("low power idle task started");
|
|
|
|
while (1) {
|
|
/* Disable interrupts */
|
|
interrupt_disable();
|
|
/* Check if the EC can enter deep doze mode or not */
|
|
if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
|
|
/* reset low power mode hw timer */
|
|
IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1);
|
|
sleep_mode_t0 = get_time();
|
|
#ifdef CONFIG_HOSTCMD_X86
|
|
/* enable lpc access wui */
|
|
task_enable_irq(IT83XX_IRQ_WKINTAD);
|
|
#endif
|
|
/* enable uart wui */
|
|
uart_enter_dsleep();
|
|
/* enable hw timer for deep doze / sleep mode wake-up */
|
|
clock_htimer_enable();
|
|
/* deep doze mode */
|
|
clock_ec_pll_ctrl(EC_PLL_DEEP_DOZE);
|
|
idle_sleep_cnt++;
|
|
} else {
|
|
/* doze mode */
|
|
clock_ec_pll_ctrl(EC_PLL_DOZE);
|
|
idle_doze_cnt++;
|
|
}
|
|
clock_cpu_standby();
|
|
interrupt_enable();
|
|
}
|
|
}
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|
|
|
|
#ifdef CONFIG_LOW_POWER_IDLE
|
|
#ifdef CONFIG_CMD_IDLE_STATS
|
|
/**
|
|
* Print low power idle statistics
|
|
*/
|
|
static int command_idle_stats(int argc, char **argv)
|
|
{
|
|
timestamp_t ts = get_time();
|
|
|
|
ccprintf("Num idle calls that doze: %d\n", idle_doze_cnt);
|
|
ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt);
|
|
|
|
ccprintf("Total Time spent in sleep(sec): %.6ld(s)\n",
|
|
total_idle_sleep_time_us);
|
|
ccprintf("Total time on: %.6lds\n\n", ts.val);
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
|
|
"",
|
|
"Print last idle stats");
|
|
|
|
#endif /* CONFIG_CMD_IDLE_STATS */
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|