111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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#if defined(CHIP_FAMILY_IT8320) /* N8 core */
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#include "config_chip_it8320.h"
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#elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */
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#include "config_chip_it8xxx2.h"
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#else
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#error "Unsupported chip family!"
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#endif
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/* Number of IRQ vectors on the IVIC */
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#define CONFIG_IRQ_COUNT IT83XX_IRQ_COUNT
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 500
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* Default PLL frequency. */
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#define PLL_CLOCK 48000000
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/* Number of I2C ports */
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#define I2C_PORT_COUNT 6
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/* I2C ports on chip
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* IT83xx - There are three i2c standard ports.
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* There are three i2c enhanced ports.
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*/
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#define I2C_STANDARD_PORT_COUNT 3
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#define I2C_ENHANCED_PORT_COUNT 3
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* non-standard task stack sizes */
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#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE)
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#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
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#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE)
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#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE)
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/* Default task stack size */
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#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
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#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
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#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
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/*
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* This is the block size of the ILM on the it83xx chip.
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* The ILM for static code cache, CPU fetch instruction from
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* ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
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*/
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#define IT83XX_ILM_BLOCK_SIZE 0x00001000
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/*
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* The AAI program instruction allows continue write flash
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* until write disable instruction.
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*/
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE
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/****************************************************************************/
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/* Define our flash layout. */
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/* Memory-mapped internal flash */
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#define CONFIG_INTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Program is run directly from storage */
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#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
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/* Compute the rest of the flash params from these */
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#include "config_std_internal_flash.h"
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/****************************************************************************/
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/* H2RAM memory mapping */
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/*
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* Only it839x series and IT838x DX support mapping LPC I/O cycle 800h ~ 9FFh
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* to 0x8D800h ~ 0x8D9FFh of DLM13.
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*
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* IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh
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* to 0x80081800 ~ 0x800819FF of DLM1.
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*/
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#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE)
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#define CONFIG_H2RAM_SIZE 0x00001000
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#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800
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/****************************************************************************/
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/* Customize the build */
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#define CONFIG_FW_RESET_VECTOR
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/* Optional features present on this chip */
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#define CHIP_FAMILY_IT83XX
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#define CONFIG_ADC
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#define CONFIG_HOSTCMD_X86
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#define CONFIG_SWITCH
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/* Chip needs to do custom pre-init */
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#define CONFIG_CHIP_PRE_INIT
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#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
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#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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