130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* EC2I control module for IT83xx. */
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#ifndef __CROS_EC_EC2I_CHIP_H
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#define __CROS_EC_EC2I_CHIP_H
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#define P80L_P80LB 0
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#define P80L_P80LE 0x3F
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#define P80L_P80LC 0
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#define P80L_BRAM_BANK1_SIZE_MASK 0x3F
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/* Index list of the host interface registers of PNPCFG */
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enum host_pnpcfg_index {
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/* Logical Device Number */
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HOST_INDEX_LDN = 0x07,
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/* Chip ID Byte 1 */
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HOST_INDEX_CHIPID1 = 0x20,
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/* Chip ID Byte 2 */
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HOST_INDEX_CHIPID2 = 0x21,
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/* Chip Version */
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HOST_INDEX_CHIPVER = 0x22,
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/* Super I/O Control */
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HOST_INDEX_SIOCTRL = 0x23,
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/* Super I/O IRQ Configuration */
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HOST_INDEX_SIOIRQ = 0x25,
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/* Super I/O General Purpose */
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HOST_INDEX_SIOGP = 0x26,
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/* Super I/O Power Mode */
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HOST_INDEX_SIOPWR = 0x2D,
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/* Depth 2 I/O Address */
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HOST_INDEX_D2ADR = 0x2E,
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/* Depth 2 I/O Data */
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HOST_INDEX_D2DAT = 0x2F,
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/* Logical Device Activate Register */
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HOST_INDEX_LDA = 0x30,
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/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
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HOST_INDEX_IOBAD0_MSB = 0x60,
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/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
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HOST_INDEX_IOBAD0_LSB = 0x61,
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/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
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HOST_INDEX_IOBAD1_MSB = 0x62,
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/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
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HOST_INDEX_IOBAD1_LSB = 0x63,
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/* Interrupt Request Number and Wake-Up on IRQ Enabled */
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HOST_INDEX_IRQNUMX = 0x70,
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/* Interrupt Request Type Select */
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HOST_INDEX_IRQTP = 0x71,
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/* DMA Channel Select 0 */
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HOST_INDEX_DMAS0 = 0x74,
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/* DMA Channel Select 1 */
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HOST_INDEX_DMAS1 = 0x75,
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/* Device Specific Logical Device Configuration 1 to 10 */
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HOST_INDEX_DSLDC1 = 0xF0,
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HOST_INDEX_DSLDC2 = 0xF1,
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HOST_INDEX_DSLDC3 = 0xF2,
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HOST_INDEX_DSLDC4 = 0xF3,
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HOST_INDEX_DSLDC5 = 0xF4,
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HOST_INDEX_DSLDC6 = 0xF5,
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HOST_INDEX_DSLDC7 = 0xF6,
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HOST_INDEX_DSLDC8 = 0xF7,
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HOST_INDEX_DSLDC9 = 0xF8,
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HOST_INDEX_DSLDC10 = 0xF9,
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};
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/* List of logical device number (LDN) assignments */
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enum logical_device_number {
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/* Serial Port 1 */
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LDN_UART1 = 0x01,
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/* Serial Port 2 */
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LDN_UART2 = 0x02,
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/* System Wake-Up Control */
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LDN_SWUC = 0x04,
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/* KBC/Mouse Interface */
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LDN_KBC_MOUSE = 0x05,
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/* KBC/Keyboard Interface */
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LDN_KBC_KEYBOARD = 0x06,
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/* Consumer IR */
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LDN_CIR = 0x0A,
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/* Shared Memory/Flash Interface */
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LDN_SMFI = 0x0F,
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/* RTC-like Timer */
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LDN_RTCT = 0x10,
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/* Power Management I/F Channel 1 */
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LDN_PMC1 = 0x11,
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/* Power Management I/F Channel 2 */
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LDN_PMC2 = 0x12,
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/* Serial Peripheral Interface */
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LDN_SSPI = 0x13,
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/* Platform Environment Control Interface */
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LDN_PECI = 0x14,
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/* Power Management I/F Channel 3 */
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LDN_PMC3 = 0x17,
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/* Power Management I/F Channel 4 */
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LDN_PMC4 = 0x18,
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/* Power Management I/F Channel 5 */
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LDN_PMC5 = 0x19,
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};
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/* EC2I read/write message */
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enum ec2i_message {
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/* EC2I write success */
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EC2I_WRITE_SUCCESS = 0x00,
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/* EC2I write error */
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EC2I_WRITE_ERROR = 0x01,
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/* EC2I read success */
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EC2I_READ_SUCCESS = 0x8000,
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/* EC2I read error */
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EC2I_READ_ERROR = 0x8100,
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};
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/* Data structure for initializing PNPCFG via ec2i. */
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struct ec2i_t {
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/* index port */
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enum host_pnpcfg_index index_port;
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/* data port */
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uint8_t data_port;
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};
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/* EC2I write */
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enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);
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/* EC2I read */
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enum ec2i_message ec2i_read(enum host_pnpcfg_index index);
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#endif /* __CROS_EC_EC2I_CHIP_H */
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