275 lines
7.2 KiB
C
275 lines
7.2 KiB
C
/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* LM4-specific ADC module for Chrome EC */
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#include "adc.h"
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#include "adc_chip.h"
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#include "atomic.h"
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#include "clock.h"
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#include "console.h"
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Maximum time we allow for an ADC conversion */
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#define ADC_TIMEOUT_US SECOND
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static volatile task_id_t task_waiting_on_ss[LM4_ADC_SEQ_COUNT];
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static void configure_gpio(void)
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{
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int i, port, mask;
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/* Use analog function for AIN */
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for (i = 0; i < ADC_CH_COUNT; ++i) {
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if (adc_channels[i].gpio_mask) {
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mask = adc_channels[i].gpio_mask;
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port = adc_channels[i].gpio_port;
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LM4_GPIO_DEN(port) &= ~mask;
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LM4_GPIO_AMSEL(port) |= mask;
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}
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}
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}
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/**
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* Flush an ADC sequencer and initiate a read.
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*
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* @param seq Sequencer to read
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* @return Raw ADC value.
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*/
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static int flush_and_read(enum lm4_adc_sequencer seq)
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{
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/*
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* This is currently simple because we can dedicate a sequencer to each
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* ADC channel. If we have enough channels that's no longer possible,
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* this code will need to become more complex. For example, we could:
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*
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* 1) Read them all using a timer interrupt, and then return the most
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* recent value? This is lowest-latency for the caller, but won't
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* return accurate data if read frequently.
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*
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* 2) Reserve SS3 for reading a single value, and configure it on each
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* read? Needs mutex if we could have multiple callers; doesn't matter
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* if just used for debugging.
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*
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* 3) Both?
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*/
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volatile uint32_t scratch __attribute__((unused));
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int event;
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/* Empty the FIFO of any previous results */
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while (!(LM4_ADC_SSFSTAT(seq) & 0x100))
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scratch = LM4_ADC_SSFIFO(seq);
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/*
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* This assumes we don't have multiple tasks accessing the same
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* sequencer. Add mutex lock if needed.
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*/
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task_waiting_on_ss[seq] = task_get_current();
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/* Clear the interrupt status */
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LM4_ADC_ADCISC |= 0x01 << seq;
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/* Enable interrupt */
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LM4_ADC_ADCIM |= 0x01 << seq;
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/* Initiate sample sequence */
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LM4_ADC_ADCPSSI |= 0x01 << seq;
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/* Wait for interrupt */
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event = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
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/* Disable interrupt */
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LM4_ADC_ADCIM &= ~(0x01 << seq);
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task_waiting_on_ss[seq] = TASK_ID_INVALID;
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if (!(event & TASK_EVENT_ADC_DONE))
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return ADC_READ_ERROR;
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/* Read the FIFO and convert to temperature */
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return LM4_ADC_SSFIFO(seq);
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}
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/**
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* Configure an ADC sequencer to be dedicated for an ADC input.
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*
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* @param seq Sequencer to configure
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* @param ain_id ADC input to use
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* @param ssctl Value for sampler sequencer control register
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*
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*/
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static void adc_configure(const struct adc_t *adc)
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{
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const enum lm4_adc_sequencer seq = adc->sequencer;
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/* Configure sample sequencer */
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LM4_ADC_ADCACTSS &= ~(0x01 << seq);
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/* Trigger sequencer by processor request */
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LM4_ADC_ADCEMUX = (LM4_ADC_ADCEMUX & ~(0xf << (seq * 4))) | 0x00;
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/* Sample internal temp sensor */
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if (adc->channel == LM4_AIN_NONE) {
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LM4_ADC_SSMUX(seq) = 0x00;
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LM4_ADC_SSEMUX(seq) = 0x00;
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} else {
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LM4_ADC_SSMUX(seq) = adc->channel & 0xf;
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LM4_ADC_SSEMUX(seq) = adc->channel >> 4;
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}
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LM4_ADC_SSCTL(seq) = adc->flag;
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/* Enable sample sequencer */
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LM4_ADC_ADCACTSS |= 0x01 << seq;
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}
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int adc_read_channel(enum adc_channel ch)
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{
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const struct adc_t *adc = adc_channels + ch;
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static uint32_t ch_busy_mask;
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static struct mutex adc_clock;
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int rv;
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/*
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* TODO(crbug.com/314121): Generalize ADC reads such that any task can
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* trigger a read of any channel.
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*/
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/*
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* Enable ADC clock and set a bit in ch_busy_mask to signify that this
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* channel is busy. Note, this function may be called from multiple
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* tasks, but each channel may be read by only one task. If assert
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* fails, then it means multiple tasks are trying to read same channel.
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*/
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mutex_lock(&adc_clock);
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ASSERT(!(ch_busy_mask & (1UL << ch)));
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clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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ch_busy_mask |= (1UL << ch);
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mutex_unlock(&adc_clock);
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rv = flush_and_read(adc->sequencer);
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/*
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* If no ADC channels are busy, then disable ADC clock to conserve
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* power.
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*/
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mutex_lock(&adc_clock);
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ch_busy_mask &= ~(1UL << ch);
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if (!ch_busy_mask)
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clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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mutex_unlock(&adc_clock);
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if (rv == ADC_READ_ERROR)
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return ADC_READ_ERROR;
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return rv * adc->factor_mul / adc->factor_div + adc->shift;
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}
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/*****************************************************************************/
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/* Interrupt handlers */
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/**
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* Handle an interrupt on the specified sample sequencer.
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*/
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static void handle_interrupt(int ss)
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{
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int id = task_waiting_on_ss[ss];
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/* Clear the interrupt status */
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LM4_ADC_ADCISC = (0x1 << ss);
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/* Wake up the task which was waiting on the interrupt, if any */
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if (id != TASK_ID_INVALID)
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task_set_event(id, TASK_EVENT_ADC_DONE, 0);
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}
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void ss0_interrupt(void) { handle_interrupt(0); }
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void ss1_interrupt(void) { handle_interrupt(1); }
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void ss2_interrupt(void) { handle_interrupt(2); }
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void ss3_interrupt(void) { handle_interrupt(3); }
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DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
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DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
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DECLARE_IRQ(LM4_IRQ_ADC0_SS2, ss2_interrupt, 2);
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DECLARE_IRQ(LM4_IRQ_ADC0_SS3, ss3_interrupt, 2);
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/*****************************************************************************/
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/* Console commands */
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#ifdef CONFIG_CMD_ECTEMP
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static int command_ectemp(int argc, char **argv)
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{
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int t = adc_read_channel(ADC_CH_EC_TEMP);
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ccprintf("EC temperature is %d K = %d C\n", t, K_TO_C(t));
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(ectemp, command_ectemp,
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NULL,
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"Print EC temperature");
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#endif
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/*****************************************************************************/
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/* Initialization */
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static void adc_init(void)
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{
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int i;
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/* Configure GPIOs */
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configure_gpio();
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/*
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* Temporarily enable the PLL when turning on the clock to the ADC
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* module, to work around chip errata (10.4). No need to notify
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* other modules; the PLL isn't enabled long enough to matter.
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*/
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clock_enable_pll(1, 0);
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/* Enable ADC0 module in run and sleep modes. */
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clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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/*
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* Use external voltage references (VREFA+, VREFA-) instead of
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* VDDA and GNDA.
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*/
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LM4_ADC_ADCCTL = 0x01;
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/* Use internal oscillator */
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LM4_ADC_ADCCC = 0x1;
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/* Disable the PLL now that the ADC is using the internal oscillator */
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clock_enable_pll(0, 0);
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/* No tasks waiting yet */
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for (i = 0; i < LM4_ADC_SEQ_COUNT; i++)
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task_waiting_on_ss[i] = TASK_ID_INVALID;
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/* Enable IRQs */
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task_enable_irq(LM4_IRQ_ADC0_SS0);
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task_enable_irq(LM4_IRQ_ADC0_SS1);
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task_enable_irq(LM4_IRQ_ADC0_SS2);
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task_enable_irq(LM4_IRQ_ADC0_SS3);
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/* 2**6 = 64x oversampling */
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LM4_ADC_ADCSAC = 6;
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/* Initialize ADC sequencer */
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for (i = 0; i < ADC_CH_COUNT; ++i)
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adc_configure(adc_channels + i);
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/* Disable ADC0 module until it is needed to conserve power. */
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clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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}
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DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
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