755 lines
20 KiB
C
755 lines
20 KiB
C
/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "util.h"
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#include "watchdog.h"
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/* Console output macros */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#define PLL_CLOCK 66666667 /* System clock = 200MHz PLL/3 = 66.667MHz */
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#ifdef CONFIG_LOW_POWER_USE_LFIOSC
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/*
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* Length of time for the processor to wake up from deep sleep. Actual
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* measurement gives anywhere up to 780us, depending on the mode it is coming
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* out of. The datasheet gives a maximum of 846us, for coming out of deep
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* sleep in our worst case deep sleep mode.
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*/
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#define DEEP_SLEEP_RECOVER_TIME_USEC 850
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#else
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/*
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* Length of time for the processor to wake up from deep sleep. Datasheet
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* maximum is 145us, but in practice have seen as much as 336us.
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*/
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#define DEEP_SLEEP_RECOVER_TIME_USEC 400
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#endif
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/* Low power idle statistics */
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#ifdef CONFIG_LOW_POWER_IDLE
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static int idle_sleep_cnt;
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static int idle_dsleep_cnt;
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static uint64_t idle_dsleep_time_us;
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static int dsleep_recovery_margin_us = 1000000;
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/*
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* Fixed amount of time to keep the console in use flag true after boot in
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* order to give a permanent window in which the low speed clock is not used.
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*/
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#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
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static int console_in_use_timeout_sec = 60;
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static timestamp_t console_expire_time;
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#endif
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static int freq;
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/**
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* Disable the PLL; run off internal oscillator.
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*/
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static void disable_pll(void)
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{
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/* Switch to 16MHz internal oscillator and power down the PLL */
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LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(0) |
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LM4_SYSTEM_RCC_BYPASS |
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LM4_SYSTEM_RCC_PWRDN |
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LM4_SYSTEM_RCC_OSCSRC(1) |
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LM4_SYSTEM_RCC_MOSCDIS;
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#ifdef CONFIG_LOW_POWER_IDLE
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/*
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* If using the low power idle, then set the ACG bit, which specifies
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* that the sleep and deep sleep modes are using their own clock gating
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* registers SCGC and DCGS respectively instead of using the run mode
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* clock gating registers RCGC.
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*/
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LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
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#endif
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LM4_SYSTEM_RCC2 &= ~LM4_SYSTEM_RCC2_USERCC2;
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freq = INTERNAL_CLOCK;
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}
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/**
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* Enable the PLL to run at full clock speed.
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*/
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static void enable_pll(void)
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{
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/* Disable the PLL so we can reconfigure it */
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disable_pll();
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/*
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* Enable the PLL (PWRDN is no longer set) and set divider. PLL is
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* still bypassed, since it hasn't locked yet.
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*/
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LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(2) |
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LM4_SYSTEM_RCC_USESYSDIV |
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LM4_SYSTEM_RCC_BYPASS |
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LM4_SYSTEM_RCC_OSCSRC(1) |
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LM4_SYSTEM_RCC_MOSCDIS;
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#ifdef CONFIG_LOW_POWER_IDLE
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/*
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* If using the low power idle, then set the ACG bit, which specifies
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* that the sleep and deep sleep modes are using their own clock gating
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* registers SCGC and DCGS respectively instead of using the run mode
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* clock gating registers RCGC.
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*/
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LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
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#endif
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/* Wait for the PLL to lock */
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clock_wait_cycles(1024);
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while (!(LM4_SYSTEM_PLLSTAT & 1))
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;
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/* Remove bypass on PLL */
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LM4_SYSTEM_RCC &= ~LM4_SYSTEM_RCC_BYPASS;
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freq = PLL_CLOCK;
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}
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void clock_enable_pll(int enable, int notify)
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{
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if (enable)
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enable_pll();
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else
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disable_pll();
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/* Notify modules of frequency change */
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if (notify)
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hook_notify(HOOK_FREQ_CHANGE);
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}
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void clock_wait_cycles(uint32_t cycles)
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{
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asm volatile("1: subs %0, #1\n"
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" bne 1b\n" : "+r"(cycles));
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}
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int clock_get_freq(void)
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{
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return freq;
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}
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void clock_init(void)
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{
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#ifdef BOARD_BDS
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/*
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* Perform an auto calibration of the internal oscillator using the
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* 32.768KHz hibernate clock, unless we've already done so. This is
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* only necessary on A2 silicon as on BDS; A3 silicon is all
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* factory-trimmed.
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*/
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if ((LM4_SYSTEM_PIOSCSTAT & 0x300) != 0x100) {
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/* Start calibration */
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LM4_SYSTEM_PIOSCCAL = 0x80000000;
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LM4_SYSTEM_PIOSCCAL = 0x80000200;
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/* Wait for result */
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clock_wait_cycles(16);
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while (!(LM4_SYSTEM_PIOSCSTAT & 0x300))
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;
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}
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#else
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/*
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* Only BDS has an external crystal; other boards don't have one, and
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* can disable main oscillator control to reduce power consumption.
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*/
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LM4_SYSTEM_MOSCCTL = 0x04;
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#endif
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/* Make sure PLL is disabled */
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disable_pll();
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}
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void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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if (mode & CGC_MODE_RUN)
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*(LM4_SYSTEM_RCGC_BASE + offset) |= mask;
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if (mode & CGC_MODE_SLEEP)
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*(LM4_SYSTEM_SCGC_BASE + offset) |= mask;
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if (mode & CGC_MODE_DSLEEP)
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*(LM4_SYSTEM_DCGC_BASE + offset) |= mask;
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/* Wait for clock change to take affect. */
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clock_wait_cycles(3);
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}
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void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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if (mode & CGC_MODE_RUN)
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*(LM4_SYSTEM_RCGC_BASE + offset) &= ~mask;
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if (mode & CGC_MODE_SLEEP)
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*(LM4_SYSTEM_SCGC_BASE + offset) &= ~mask;
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if (mode & CGC_MODE_DSLEEP)
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*(LM4_SYSTEM_DCGC_BASE + offset) &= ~mask;
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}
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/*
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* The low power idle task does not support using the EEPROM,
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* because it is dangerous to go to deep sleep while EEPROM
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* transaction is in progress. To fix, LM4_EEPROM_EEDONE, should
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* be checked before going in to deep sleep.
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*/
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#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_EEPROM)
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#error "Low power idle mode does not support use of EEPROM"
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#endif
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#ifdef CONFIG_LOW_POWER_IDLE
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void clock_refresh_console_in_use(void)
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{
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disable_sleep(SLEEP_MASK_CONSOLE);
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/* Set console in use expire time. */
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console_expire_time = get_time();
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console_expire_time.val += console_in_use_timeout_sec * SECOND;
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}
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/* Low power idle task. Executed when no tasks are ready to be scheduled. */
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void __idle(void)
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{
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timestamp_t t0, t1, rtc_t0, rtc_t1;
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int next_delay = 0;
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int time_for_dsleep, margin_us;
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int use_low_speed_clock;
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/* Enable the hibernate IRQ used to wake up from deep sleep */
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system_enable_hib_interrupt();
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/* Set SRAM and flash power management to 'low power' in deep sleep. */
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LM4_SYSTEM_DSLPPWRCFG = 0x23;
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/* Enable JTAG interrupt which will notify us when JTAG is in use. */
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gpio_enable_interrupt(GPIO_JTAG_TCK);
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/*
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* Initialize console in use to true and specify the console expire
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* time in order to give a fixed window on boot in which the low speed
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* clock will not be used in idle.
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*/
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disable_sleep(SLEEP_MASK_CONSOLE);
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console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
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/*
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* Print when the idle task starts. This is the lowest priority task,
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* so this only starts once all other tasks have gotten a chance to do
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* their task inits and have gone to sleep.
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*/
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CPRINTS("low power idle task started");
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while (1) {
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/*
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* Disable interrupts before going to deep sleep in order to
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* calculate the appropriate time to wake up. Note: the wfi
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* instruction waits until an interrupt is pending, so it
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* will still wake up even with interrupts disabled.
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*/
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interrupt_disable();
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t0 = get_time();
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next_delay = __hw_clock_event_get() - t0.le.lo;
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/* Do we have enough time before next event to deep sleep. */
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time_for_dsleep = next_delay > (DEEP_SLEEP_RECOVER_TIME_USEC +
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HIB_SET_RTC_MATCH_DELAY_USEC);
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if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
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/* Deep-sleep in STOP mode. */
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idle_dsleep_cnt++;
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/* Check if the console use has expired. */
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if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
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t0.val > console_expire_time.val) {
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/* Enable low speed deep sleep. */
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enable_sleep(SLEEP_MASK_CONSOLE);
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/*
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* Wait one clock before checking if low speed
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* deep sleep is allowed to give time for
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* sleep mask to update.
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*/
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clock_wait_cycles(1);
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if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
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CPRINTS("Disabling console in "
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"deep sleep");
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}
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/*
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* Determine if we should use a lower clock speed or
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* keep the same (16MHz) clock in deep sleep. Use the
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* lower speed only if the sleep mask specifies that low
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* speed sleep is allowed, the console UART TX is not
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* busy, and the console UART buffer is empty.
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*/
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use_low_speed_clock = LOW_SPEED_DEEP_SLEEP_ALLOWED &&
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!uart_tx_in_progress() && uart_buffer_empty();
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#ifdef CONFIG_LOW_POWER_USE_LFIOSC
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/* Set the deep sleep clock register. Use either the
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* normal PIOSC (16MHz) or the LFIOSC (32kHz). */
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LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
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0x32 : 0x10;
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#else
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/*
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* Set the deep sleep clock register. Use either the
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* PIOSC with no divider (16MHz) or the PIOSC with
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* a /64 divider (250kHz).
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*/
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LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
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0x1f800010 : 0x10;
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#endif
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/*
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* If using low speed clock, disable console.
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* This will also convert the console RX pin to a GPIO
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* and set an edge interrupt to wake us from deep sleep
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* if any action occurs on console.
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*/
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if (use_low_speed_clock)
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uart_enter_dsleep();
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/* Set deep sleep bit. */
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CPU_SCB_SYSCTRL |= 0x4;
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/* Record real time before sleeping. */
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rtc_t0 = system_get_rtc();
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/*
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* Set RTC interrupt in time to wake up before
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* next event.
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*/
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system_set_rtc_alarm(0, next_delay -
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DEEP_SLEEP_RECOVER_TIME_USEC);
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/* Wait for interrupt: goes into deep sleep. */
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asm("wfi");
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/* Clear deep sleep bit. */
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CPU_SCB_SYSCTRL &= ~0x4;
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/* Disable and clear RTC interrupt. */
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system_reset_rtc_alarm();
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/* Fast forward timer according to RTC counter. */
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rtc_t1 = system_get_rtc();
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t1.val = t0.val + (rtc_t1.val - rtc_t0.val);
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force_time(t1);
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/* If using low speed clock, re-enable the console. */
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if (use_low_speed_clock)
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uart_exit_dsleep();
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/* Record time spent in deep sleep. */
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idle_dsleep_time_us += (rtc_t1.val - rtc_t0.val);
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/* Calculate how close we were to missing deadline */
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margin_us = next_delay - (int)(rtc_t1.val - rtc_t0.val);
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if (margin_us < 0)
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CPRINTS("overslept by %dus", -margin_us);
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/* Record the closest to missing a deadline. */
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if (margin_us < dsleep_recovery_margin_us)
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dsleep_recovery_margin_us = margin_us;
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} else {
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idle_sleep_cnt++;
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/* Normal idle : only CPU clock stopped. */
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asm("wfi");
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}
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interrupt_enable();
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}
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}
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#endif /* CONFIG_LOW_POWER_IDLE */
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/*****************************************************************************/
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/* Console commands */
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#ifdef CONFIG_CMD_SLEEP
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/**
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* Measure baseline for power consumption.
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*
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* Levels :
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* 0 : CPU running in tight loop
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* 1 : CPU running in tight loop but peripherals gated
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* 2 : CPU in sleep mode
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* 3 : CPU in sleep mode and peripherals gated
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* 4 : CPU in deep sleep mode
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* 5 : CPU in deep sleep mode and peripherals gated
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*
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* Clocks :
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* 0 : No change
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* 1 : 16MHz
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* 2 : 1 MHz
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* 3 : 30kHz
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*
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* SRAM Power Management:
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* 0 : Active
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* 1 : Standby
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* 3 : Low Power
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*
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* Flash Power Management:
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* 0 : Active
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* 2 : Low Power
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*/
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static int command_sleep(int argc, char **argv)
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{
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int level = 0;
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int clock = 0;
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int sram_pm = 0;
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int flash_pm = 0;
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uint32_t uartibrd = 0;
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uint32_t uartfbrd = 0;
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if (argc >= 2)
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level = strtoi(argv[1], NULL, 10);
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if (argc >= 3)
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clock = strtoi(argv[2], NULL, 10);
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if (argc >= 4)
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sram_pm = strtoi(argv[3], NULL, 10);
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if (argc >= 5)
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flash_pm = strtoi(argv[4], NULL, 10);
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#ifdef BOARD_BDS
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/* Remove LED current sink. */
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gpio_set_level(GPIO_DEBUG_LED, 0);
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#endif
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ccprintf("Sleep : level %d, clock %d, sram pm %d, flash_pm %d...\n",
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level, clock, sram_pm, flash_pm);
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cflush();
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/* Set clock speed. */
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if (clock) {
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/* Use ROM code function to set the clock */
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void **func_table = (void **)*(uint32_t *)0x01000044;
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void (*rom_clock_set)(uint32_t rcc) = func_table[23];
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/* Disable interrupts. */
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asm volatile("cpsid i");
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switch (clock) {
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case 1: /* 16MHz IOSC */
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uartibrd = 17;
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uartfbrd = 23;
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rom_clock_set(0x00000d51);
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break;
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case 2: /* 1MHz IOSC */
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uartibrd = 1;
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uartfbrd = 5;
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rom_clock_set(0x07C00d51);
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break;
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case 3: /* 30 kHz */
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uartibrd = 0;
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uartfbrd = 0;
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rom_clock_set(0x00000d71);
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break;
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}
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/*
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* TODO(crosbug.com/p/23795): move this to the UART module;
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* ugly to have UARTisms here. Also note this only fixes
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* UART0, not UART1. Should just be able to trigger
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* HOOK_FREQ_CHANGE and have that take care of it.
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*/
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if (uartfbrd) {
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/* Disable the port via UARTCTL and add HSE. */
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LM4_UART_CTL(0) = 0x0320;
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/* Set the baud rate divisor. */
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LM4_UART_IBRD(0) = uartibrd;
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LM4_UART_FBRD(0) = uartfbrd;
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/* Poke UARTLCRH to make the new divisor take effect. */
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LM4_UART_LCRH(0) = LM4_UART_LCRH(0);
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/* Enable the port. */
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LM4_UART_CTL(0) |= 0x0001;
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}
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asm volatile("cpsie i");
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}
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if (uartfbrd) {
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ccprintf("We are still alive. RCC=%08x\n", LM4_SYSTEM_RCC);
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cflush();
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}
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/* Enable interrupts. */
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asm volatile("cpsid i");
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/* gate peripheral clocks */
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if (level & 1) {
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clock_disable_peripheral(CGC_OFFSET_WD, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_TIMER, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_GPIO, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_DMA, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_HIB, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_UART, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_SSI, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_I2C, 0xffffffff,
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CGC_MODE_ALL);
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clock_disable_peripheral(CGC_OFFSET_ADC, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
clock_disable_peripheral(CGC_OFFSET_LPC, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
clock_disable_peripheral(CGC_OFFSET_PECI, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
clock_disable_peripheral(CGC_OFFSET_FAN, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
clock_disable_peripheral(CGC_OFFSET_EEPROM, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
clock_disable_peripheral(CGC_OFFSET_WTIMER, 0xffffffff,
|
|
CGC_MODE_ALL);
|
|
}
|
|
|
|
/* Set deep sleep bit. */
|
|
if (level >= 4)
|
|
CPU_SCB_SYSCTRL |= 0x4;
|
|
|
|
/* Set SRAM and flash PM for sleep and deep sleep. */
|
|
LM4_SYSTEM_SLPPWRCFG = (flash_pm << 4) | sram_pm;
|
|
LM4_SYSTEM_DSLPPWRCFG = (flash_pm << 4) | sram_pm;
|
|
|
|
/* Go to low power mode (forever ...) */
|
|
if (level > 1)
|
|
while (1) {
|
|
asm("wfi");
|
|
watchdog_reload();
|
|
}
|
|
else
|
|
while (1)
|
|
watchdog_reload();
|
|
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(sleep, command_sleep,
|
|
"[level [clock] [sram pm] [flash pm]]",
|
|
"Drop into sleep");
|
|
#endif /* CONFIG_CMD_SLEEP */
|
|
|
|
#ifdef CONFIG_CMD_PLL
|
|
|
|
static int command_pll(int argc, char **argv)
|
|
{
|
|
int v;
|
|
|
|
/* Toggle the PLL */
|
|
if (argc > 1) {
|
|
if (parse_bool(argv[1], &v)) {
|
|
clock_enable_pll(v, 1);
|
|
} else {
|
|
/* Disable PLL and set extra divider */
|
|
char *e;
|
|
v = strtoi(argv[1], &e, 10);
|
|
if (*e)
|
|
return EC_ERROR_PARAM1;
|
|
|
|
LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(v - 1) |
|
|
LM4_SYSTEM_RCC_BYPASS |
|
|
LM4_SYSTEM_RCC_PWRDN |
|
|
LM4_SYSTEM_RCC_OSCSRC(1) |
|
|
LM4_SYSTEM_RCC_MOSCDIS;
|
|
|
|
freq = INTERNAL_CLOCK / v;
|
|
|
|
/* Notify modules of frequency change */
|
|
hook_notify(HOOK_FREQ_CHANGE);
|
|
}
|
|
}
|
|
|
|
/* Print current PLL state */
|
|
ccprintf("RCC: 0x%08x\n", LM4_SYSTEM_RCC);
|
|
ccprintf("RCC2: 0x%08x\n", LM4_SYSTEM_RCC2);
|
|
ccprintf("PLLSTAT: 0x%08x\n", LM4_SYSTEM_PLLSTAT);
|
|
ccprintf("Clock: %d Hz\n", clock_get_freq());
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(pll, command_pll,
|
|
"[ on | off | <div> ]",
|
|
"Get/set PLL state");
|
|
|
|
#endif /* CONFIG_CMD_PLL */
|
|
|
|
#ifdef CONFIG_CMD_CLOCKGATES
|
|
/**
|
|
* Print all clock gating registers
|
|
*/
|
|
static int command_clock_gating(int argc, char **argv)
|
|
{
|
|
ccprintf(" Run , Sleep , Deep Sleep\n");
|
|
|
|
ccprintf("WD: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WD));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WD));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WD));
|
|
|
|
ccprintf("TIMER: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_TIMER));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_TIMER));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_TIMER));
|
|
|
|
ccprintf("GPIO: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_GPIO));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_GPIO));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_GPIO));
|
|
|
|
ccprintf("DMA: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_DMA));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_DMA));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_DMA));
|
|
|
|
ccprintf("HIB: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_HIB));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_HIB));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_HIB));
|
|
|
|
ccprintf("UART: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_UART));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_UART));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_UART));
|
|
|
|
ccprintf("SSI: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_SSI));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_SSI));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_SSI));
|
|
|
|
ccprintf("I2C: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_I2C));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_I2C));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_I2C));
|
|
|
|
ccprintf("ADC: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_ADC));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_ADC));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_ADC));
|
|
|
|
ccprintf("LPC: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_LPC));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_LPC));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_LPC));
|
|
|
|
ccprintf("PECI: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_PECI));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_PECI));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_PECI));
|
|
|
|
ccprintf("FAN: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_FAN));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_FAN));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_FAN));
|
|
|
|
ccprintf("EEPROM: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_EEPROM));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_EEPROM));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_EEPROM));
|
|
|
|
ccprintf("WTIMER: 0x%08x, ",
|
|
*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WTIMER));
|
|
ccprintf("0x%08x, ", *(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WTIMER));
|
|
ccprintf("0x%08x\n", *(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WTIMER));
|
|
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(clockgates, command_clock_gating,
|
|
"",
|
|
"Get state of the clock gating controls regs");
|
|
#endif /* CONFIG_CMD_CLOCKGATES */
|
|
|
|
#ifdef CONFIG_LOW_POWER_IDLE
|
|
/**
|
|
* Print low power idle statistics
|
|
*/
|
|
static int command_idle_stats(int argc, char **argv)
|
|
{
|
|
timestamp_t ts = get_time();
|
|
|
|
ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt);
|
|
ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt);
|
|
ccprintf("Time spent in deep-sleep: %.6lds\n",
|
|
idle_dsleep_time_us);
|
|
ccprintf("Total time on: %.6lds\n", ts.val);
|
|
ccprintf("Deep-sleep closest to wake deadline: %dus\n",
|
|
dsleep_recovery_margin_us);
|
|
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
|
|
"",
|
|
"Print last idle stats");
|
|
|
|
/**
|
|
* Configure deep sleep clock settings.
|
|
*/
|
|
static int command_dsleep(int argc, char **argv)
|
|
{
|
|
int v;
|
|
|
|
if (argc > 1) {
|
|
if (parse_bool(argv[1], &v)) {
|
|
/*
|
|
* Force deep sleep not to use low speed clock or
|
|
* allow it to use the low speed clock.
|
|
*/
|
|
if (v)
|
|
disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
|
else
|
|
enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
|
|
} else {
|
|
/* Set console in use timeout. */
|
|
char *e;
|
|
v = strtoi(argv[1], &e, 10);
|
|
if (*e)
|
|
return EC_ERROR_PARAM1;
|
|
|
|
console_in_use_timeout_sec = v;
|
|
|
|
/* Refresh console in use to use new timeout. */
|
|
clock_refresh_console_in_use();
|
|
}
|
|
}
|
|
|
|
ccprintf("Sleep mask: %08x\n", sleep_mask);
|
|
ccprintf("Console in use timeout: %d sec\n",
|
|
console_in_use_timeout_sec);
|
|
ccprintf("DSLPCLKCFG register: 0x%08x\n", LM4_SYSTEM_DSLPCLKCFG);
|
|
|
|
return EC_SUCCESS;
|
|
}
|
|
DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
|
|
"[ on | off | <timeout> sec]",
|
|
"Deep sleep clock settings:\nUse 'on' to force deep "
|
|
"sleep not to use low speed clock.\nUse 'off' to "
|
|
"allow deep sleep to auto-select using the low speed "
|
|
"clock.\n"
|
|
"Give a timeout value for the console in use timeout.\n"
|
|
"See also 'sleepmask'.");
|
|
#endif /* CONFIG_LOW_POWER_IDLE */
|
|
|