109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/cortex-m/config_core.h"
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/* 16.000 MHz internal oscillator frequency (PIOSC) */
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#define INTERNAL_CLOCK 16000000
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 132
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 8192
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 250
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* Number of I2C ports */
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#define I2C_PORT_COUNT 6
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/*
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* Time it takes to set the RTC match register. This value is conservatively
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* set based on measurements around 200us.
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*/
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#define HIB_SET_RTC_MATCH_DELAY_USEC 300
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/****************************************************************************/
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/* Memory mapping */
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE 0x00008000
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/* System stack size */
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#define CONFIG_STACK_SIZE 4096
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/* non-standard task stack sizes */
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#define IDLE_TASK_STACK_SIZE 512
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#define LARGER_TASK_STACK_SIZE 768
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#define SMALLER_TASK_STACK_SIZE 384
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/* Default task stack size */
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#define TASK_STACK_SIZE 512
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#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
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#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
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#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
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/* Ideal flash write size fills the 32-entry flash write buffer */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
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/* This is the physical size of the flash on the chip. We'll reserve one bank
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* in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
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* doesn't support a write-protect pin, and if we make the write-protection
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* permanent, it can't be undone easily enough to support RMA. */
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#define CONFIG_FLASH_SIZE 0x00040000
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/****************************************************************************/
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/* Define our flash layout. */
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/* Memory-mapped internal flash */
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#define CONFIG_INTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Program is run directly from storage */
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#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
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/* Compute the rest of the flash params from these */
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#include "config_std_internal_flash.h"
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/****************************************************************************/
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/* Lock the boot configuration to prevent brickage. */
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/*
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* No GPIO trigger for ROM bootloader.
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* Keep JTAG debugging enabled.
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* Use 0xA442 flash write key.
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* Lock it this way.
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*/
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#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
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/****************************************************************************/
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/* Customize the build */
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_HOSTCMD_ALIGNED
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#define CONFIG_HOSTCMD_LPC
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#define CONFIG_PECI
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#define CONFIG_RTC
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#define CONFIG_SWITCH
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#define CONFIG_MPU
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/* Chip needs to do custom pre-init */
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#define CONFIG_CHIP_PRE_INIT
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#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
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#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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