353 lines
8.1 KiB
C
353 lines
8.1 KiB
C
/* Copyright 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* UART module for Chrome EC */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "lpc.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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#ifdef CONFIG_UART_HOST
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#define IRQ_UART_HOST CONCAT2(LM4_IRQ_UART, CONFIG_UART_HOST)
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#endif
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static int init_done;
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int uart_init_done(void)
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{
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return init_done;
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}
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void uart_tx_start(void)
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{
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/* If interrupt is already enabled, nothing to do */
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if (LM4_UART_IM(0) & 0x20)
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return;
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/* Do not allow deep sleep while transmit in progress */
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disable_sleep(SLEEP_MASK_UART);
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/*
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* Re-enable the transmit interrupt, then forcibly trigger the
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* interrupt. This works around a hardware problem with the
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* UART where the FIFO only triggers the interrupt when its
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* threshold is _crossed_, not just met.
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*/
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LM4_UART_IM(0) |= 0x20;
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task_trigger_irq(LM4_IRQ_UART0);
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}
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void uart_tx_stop(void)
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{
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LM4_UART_IM(0) &= ~0x20;
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/* Re-allow deep sleep */
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enable_sleep(SLEEP_MASK_UART);
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}
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void uart_tx_flush(void)
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{
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/* Wait for transmit FIFO empty */
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while (!(LM4_UART_FR(0) & 0x80))
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;
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}
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int uart_tx_ready(void)
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{
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return !(LM4_UART_FR(0) & 0x20);
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}
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int uart_tx_in_progress(void)
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{
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/* Transmit is in progress if the TX busy bit is set. */
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return LM4_UART_FR(0) & 0x08;
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}
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int uart_rx_available(void)
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{
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return !(LM4_UART_FR(0) & 0x10);
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}
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void uart_write_char(char c)
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{
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/* Wait for space in transmit FIFO. */
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while (!uart_tx_ready())
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;
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LM4_UART_DR(0) = c;
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}
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int uart_read_char(void)
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{
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return LM4_UART_DR(0);
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}
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static void uart_clear_rx_fifo(int channel)
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{
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int scratch __attribute__ ((unused));
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while (!(LM4_UART_FR(channel) & 0x10))
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scratch = LM4_UART_DR(channel);
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}
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/**
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* Interrupt handler for UART0
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*/
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void uart_ec_interrupt(void)
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{
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/* Clear transmit and receive interrupt status */
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LM4_UART_ICR(0) = 0x70;
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/* Read input FIFO until empty, then fill output FIFO */
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uart_process_input();
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uart_process_output();
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}
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DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
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#ifdef CONFIG_UART_HOST
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/**
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* Interrupt handler for Host UART
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*/
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void uart_host_interrupt(void)
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{
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/* Clear transmit and receive interrupt status */
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LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
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#ifdef CONFIG_HOSTCMD_LPC
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/*
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* If we have space in our FIFO and a character is pending in LPC,
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* handle that character.
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*/
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if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x20) && lpc_comx_has_char()) {
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/* Copy the next byte then disable transmit interrupt */
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LM4_UART_DR(CONFIG_UART_HOST) = lpc_comx_get_char();
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LM4_UART_IM(CONFIG_UART_HOST) &= ~0x20;
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}
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/*
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* Handle received character. There is no flow control on input;
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* received characters are blindly forwarded to LPC. This is ok
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* because LPC is much faster than UART, and we don't have flow control
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* on the UART receive-side either.
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*/
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if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x10))
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lpc_comx_put_char(LM4_UART_DR(CONFIG_UART_HOST));
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#endif
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}
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/* Must be same prio as LPC interrupt handler so they don't preempt */
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DECLARE_IRQ(IRQ_UART_HOST, uart_host_interrupt, 2);
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#endif /* CONFIG_UART_HOST */
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static void uart_config(int port)
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{
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/* Disable the port */
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LM4_UART_CTL(port) = 0x0300;
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/* Use the internal oscillator */
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LM4_UART_CC(port) = 0x1;
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/* Set the baud rate divisor */
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LM4_UART_IBRD(port) = (INTERNAL_CLOCK / 16) / CONFIG_UART_BAUD_RATE;
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LM4_UART_FBRD(port) =
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(((INTERNAL_CLOCK / 16) % CONFIG_UART_BAUD_RATE) * 64
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+ CONFIG_UART_BAUD_RATE / 2) / CONFIG_UART_BAUD_RATE;
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/*
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* 8-N-1, FIFO enabled. Must be done after setting
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* the divisor for the new divisor to take effect.
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*/
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LM4_UART_LCRH(port) = 0x70;
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/*
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* Interrupt when RX fifo at minimum (>= 1/8 full), and TX fifo
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* when <= 1/4 full
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*/
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LM4_UART_IFLS(port) = 0x01;
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/*
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* Unmask receive-FIFO, receive-timeout. We need
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* receive-timeout because the minimum RX FIFO depth is 1/8 = 2
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* bytes; without the receive-timeout we'd never be notified
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* about single received characters.
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*/
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LM4_UART_IM(port) = 0x50;
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/* Enable the port */
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LM4_UART_CTL(port) |= 0x0001;
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}
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void uart_init(void)
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{
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uint32_t mask = 0;
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/*
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* Enable UART0 in run, sleep, and deep sleep modes. Enable the Host
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* UART in run and sleep modes.
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*/
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mask |= 1;
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clock_enable_peripheral(CGC_OFFSET_UART, mask, CGC_MODE_ALL);
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#ifdef CONFIG_UART_HOST
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mask |= BIT(CONFIG_UART_HOST);
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#endif
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clock_enable_peripheral(CGC_OFFSET_UART, mask,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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gpio_config_module(MODULE_UART, 1);
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/* Configure UARTs (identically) */
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uart_config(0);
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#ifdef CONFIG_UART_HOST
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uart_config(CONFIG_UART_HOST);
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#endif
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/*
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* Enable interrupts for UART0 only. Host UART will have to wait
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* until the LPC bus is initialized.
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*/
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uart_clear_rx_fifo(0);
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task_enable_irq(LM4_IRQ_UART0);
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init_done = 1;
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}
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#ifdef CONFIG_LOW_POWER_IDLE
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void uart_enter_dsleep(void)
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{
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const struct gpio_info g = gpio_list[GPIO_UART0_RX];
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/* Disable the UART0 module interrupt. */
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task_disable_irq(LM4_IRQ_UART0);
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/* Disable UART0 peripheral in deep sleep. */
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clock_disable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
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/*
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* Set the UART0 RX pin to be a generic GPIO with the flags defined
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* in the board.c file.
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*/
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gpio_reset(GPIO_UART0_RX);
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/* Clear any pending GPIO interrupts on the UART0 RX pin. */
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LM4_GPIO_ICR(g.port) = g.mask;
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/* Enable GPIO interrupts on the UART0 RX pin. */
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gpio_enable_interrupt(GPIO_UART0_RX);
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}
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void uart_exit_dsleep(void)
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{
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const struct gpio_info g = gpio_list[GPIO_UART0_RX];
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/*
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* If the UART0 RX GPIO interrupt has not fired, then no edge has been
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* detected. Disable the GPIO interrupt so that switching the pin over
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* to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
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* Note: we can't disable this interrupt if it has already fired
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* because then the IRQ will not get called.
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*/
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if (!(LM4_GPIO_MIS(g.port) & g.mask))
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gpio_disable_interrupt(GPIO_UART0_RX);
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/* Configure UART0 pins for use in UART peripheral. */
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gpio_config_module(MODULE_UART, 1);
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/* Clear pending interrupts on UART peripheral and enable interrupts. */
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uart_clear_rx_fifo(0);
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task_enable_irq(LM4_IRQ_UART0);
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/* Enable UART0 peripheral in deep sleep */
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clock_enable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
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}
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void uart_deepsleep_interrupt(enum gpio_signal signal)
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{
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/*
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* Activity seen on UART RX pin while UART was disabled for deep sleep.
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* The console won't see that character because the UART is disabled,
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* so we need to inform the clock module of UART activity ourselves.
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*/
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clock_refresh_console_in_use();
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/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
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gpio_disable_interrupt(GPIO_UART0_RX);
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}
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#endif /* CONFIG_LOW_POWER_IDLE */
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/*****************************************************************************/
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/* COMx functions */
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#ifdef CONFIG_UART_HOST
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void uart_comx_enable(void)
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{
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uart_clear_rx_fifo(CONFIG_UART_HOST);
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task_enable_irq(IRQ_UART_HOST);
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}
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int uart_comx_putc_ok(void)
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{
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if (LM4_UART_FR(CONFIG_UART_HOST) & 0x20) {
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/*
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* FIFO is full, so enable transmit interrupt to let us know
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* when it empties.
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*/
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LM4_UART_IM(CONFIG_UART_HOST) |= 0x20;
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return 0;
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} else {
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return 1;
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}
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}
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void uart_comx_putc(int c)
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{
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LM4_UART_DR(CONFIG_UART_HOST) = c;
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}
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#endif /* CONFIG_UART_HOST */
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/*****************************************************************************/
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/* Console commands */
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#ifdef CONFIG_CMD_COMXTEST
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/**
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* Write a character to COMx, waiting for space in the output buffer if
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* necessary.
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*/
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static void uart_comx_putc_wait(int c)
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{
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while (!uart_comx_putc_ok())
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;
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uart_comx_putc(c);
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}
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static int command_comxtest(int argc, char **argv)
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{
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/* Put characters to COMX port */
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const char *c = argc > 1 ? argv[1] : "testing comx output!";
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ccprintf("Writing \"%s\\r\\n\" to COMx UART...\n", c);
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while (*c)
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uart_comx_putc_wait(*c++);
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uart_comx_putc_wait('\r');
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uart_comx_putc_wait('\n');
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(comxtest, command_comxtest,
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"[string]",
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"Write test data to COMx uart");
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#endif /* CONFIG_CMD_COMXTEST */
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