490 lines
28 KiB
C
490 lines
28 KiB
C
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */
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#ifndef _PWRSEQ_REGS_H_
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#define _PWRSEQ_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(__ICCARM__)
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#pragma system_include
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#endif
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#if defined(__CC_ARM)
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#pragma anon_unions
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#endif
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/* **** Definitions **** */
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/**
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* mxc_pwrseq_regs_t
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* Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral
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* Module.
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*/
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/**
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* pwrseq_registers
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* Structure type to access the PWRSEQ Registers.
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*/
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typedef struct {
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__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
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__IO uint32_t
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lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
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__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
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__R uint32_t rsv_0xc_0x3f[13];
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__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
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} mxc_pwrseq_regs_t;
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/**
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* Register offsets for module PWRSEQ
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* PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
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*/
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#define MXC_R_PWRSEQ_LP_CTRL \
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((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
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\ \ \ 0x0000</tt> */
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#define MXC_R_PWRSEQ_LP_WAKEFL \
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((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
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\ \ \ 0x0004</tt> */
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#define MXC_R_PWRSEQ_LPWK_EN \
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((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
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\ \ \ 0x0008</tt> */
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#define MXC_R_PWRSEQ_LPMEMSD \
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((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
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\ \ \ 0x0040</tt> */
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/**
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* pwrseq_registers
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* Low Power Control Register.
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*/
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \
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0 /**< LP_CTRL_RAMRET_SEL0 Position */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \
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LP_CTRL_RAMRET_SEL0 \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \
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1 /**< LP_CTRL_RAMRET_SEL1 Position */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \
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LP_CTRL_RAMRET_SEL1 \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \
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2 /**< LP_CTRL_RAMRET_SEL2 Position */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \
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LP_CTRL_RAMRET_SEL2 \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \
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3 /**< LP_CTRL_RAMRET_SEL3 Position */
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#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \
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LP_CTRL_RAMRET_SEL3 \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
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(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
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#define MXC_F_PWRSEQ_LP_CTRL_OVR \
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((uint32_t)(0x3UL \
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<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
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((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
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#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \
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(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
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<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
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((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
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#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \
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(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
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<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
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((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
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#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \
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(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
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<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \
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6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \ \
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LP_CTRL_VCORE_DET_BYPASS \
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\ \
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\ \ \ \ \
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Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
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((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_DET_BYPASS_ENABLED \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
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((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_DET_BYPASS_DISABLE \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \
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8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
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\ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \
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(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \
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\ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \
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10 /**< LP_CTRL_FAST_WK_EN Position */
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#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \
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LP_CTRL_FAST_WK_EN \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
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\ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
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(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \
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\ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
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#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \
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((uint32_t)( \
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0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
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((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
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#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \
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(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
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<< MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
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((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
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#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF \
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(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
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<< MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
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* \ \
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* \ \ \
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* \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \
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12 /**< LP_CTRL_VCORE_POR_DIS Position */
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \
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LP_CTRL_VCORE_POR_DIS \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
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((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_POR_DIS_DIS \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
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((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_POR_DIS_EN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
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#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS \
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((uint32_t)(0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
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((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \
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(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \
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* \ \
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* \ \ \
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* \ \ \ \
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* \ \ \ \ \
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*/
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#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
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((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
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* \ \
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* \ \ \
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* \ \ \ \
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* \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \
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20 /**< LP_CTRL_VCORE_SVM_DIS Position */
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#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \
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LP_CTRL_VCORE_SVM_DIS \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
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((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_SVM_DIS_EN \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
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((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VCORE_SVM_DIS_DIS \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \
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25 /**< LP_CTRL_VDDIO_POR_DIS Position */
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#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \
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LP_CTRL_VDDIO_POR_DIS \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
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((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
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(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
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<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VDDIO_POR_DIS_EN \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
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((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
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#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
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(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
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<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
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LP_CTRL_VDDIO_POR_DIS_DIS \
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\ \ \ \ Setting */
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/**
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* pwrseq_registers
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* Low Power Mode Wakeup Flags for GPIO0
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*/
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#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
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#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \
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((uint32_t)( \
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0x3FFFUL \
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<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \
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\ \ \ Mask */
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/**
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* pwrseq_registers
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* Low Power I/O Wakeup Enable Register 0. This register enables low
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* power wakeup functionality for GPIO0.
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*/
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#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
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#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \
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((uint32_t)(0x3FFFUL \
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<< MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \
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\ \ \ Mask */
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/**
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* pwrseq_registers
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* Low Power Memory Shutdown Control.
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*/
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \
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0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
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((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
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((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \
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LPMEMSD_SRAM0_OFF_SHUTDOWN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \
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1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
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((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
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((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \
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LPMEMSD_SRAM1_OFF_SHUTDOWN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \
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2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
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((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
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((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \
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LPMEMSD_SRAM2_OFF_SHUTDOWN \
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\ \ \ \ Setting */
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \
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3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \
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*/
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#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \
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((uint32_t)( \
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0x1UL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \
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\ \ \ \ Mask */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
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((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \
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\ \ \ \ Setting */
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#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
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((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
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#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
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(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
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<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \
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LPMEMSD_SRAM3_OFF_SHUTDOWN \
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\ \ \ \ Setting */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _PWRSEQ_REGS_H_ */
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