71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H
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#define __CROS_EC_CONFIG_CHIP_NPCX5_H
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/*
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* NPCX5 Series Device-Specific Information
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* Ex. NPCX5(M)(N)(G)
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* @param M: 7: 132-pins package, 8: 128-pins package
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* @param N: 5: 128KB RAM Size, 6: 256KB RAM Size
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* @param G: Google EC.
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*/
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/*****************************************************************************/
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/* Hardware features */
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/* Number of UART modules. */
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#define UART_MODULE_COUNT 1
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/*
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* Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
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* additional port.
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*/
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#define CONFIG_I2C_MULTI_PORT_CONTROLLER
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/* Number of I2C controllers */
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#define I2C_CONTROLLER_COUNT 4
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/* Number of I2C ports */
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#define I2C_PORT_COUNT 5
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/*****************************************************************************/
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/* Memory mapping */
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#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
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#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
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#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */
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#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
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#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */
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#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
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/* Use chip variant to specify the size and start address of program memory */
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#if defined(CHIP_VARIANT_NPCX5M5G)
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/* 96KB RAM for FW code */
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#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024)
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/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000
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#elif defined(CHIP_VARIANT_NPCX5M6G)
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/* 224KB RAM for FW code */
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#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024)
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/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000
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#else
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#error "Unsupported chip variant"
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#endif
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/* Total RAM size checking for npcx ec */
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#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
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#if defined(CHIP_VARIANT_NPCX5M5G)
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/* 128KB RAM in NPCX5M5G */
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#if (NPCX_RAM_SIZE != 0x20000)
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#error "Wrong memory mapping layout for NPCX5M5G"
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#endif
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#elif defined(CHIP_VARIANT_NPCX5M6G)
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/* 256KB RAM in NPCX5M6G */
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#if (NPCX_RAM_SIZE != 0x40000)
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#error "Wrong memory mapping layout for NPCX5M6G"
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#endif
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#endif
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#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */
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