162 lines
3.8 KiB
C
162 lines
3.8 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* GPIO module for Chrome EC */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "gpio_chip.h"
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#include "hooks.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "util.h"
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/* Console output macros */
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#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
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/* For each EXTI bit, record which GPIO entry is using it */
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static uint8_t exti_events[16];
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void gpio_pre_init(void)
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{
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const struct gpio_info *g = gpio_list;
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int is_warm = system_is_reboot_warm();
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int i;
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/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
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#ifdef CHIP_FAMILY_STM32H7
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STM32_RCC_APB4ENR |= STM32_RCC_SYSCFGEN;
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#else
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STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
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#endif
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/* Delay 1 APB clock cycle after the clock is enabled */
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clock_wait_bus_cycles(BUS_APB, 1);
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/* Disable all GPIO EXTINTs (EXTINT0..15) left enabled after sysjump. */
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STM32_EXTI_IMR &= ~0xFFFF;
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if (!is_warm)
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gpio_enable_clocks();
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/* Set all GPIOs to defaults */
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for (i = 0; i < GPIO_COUNT; i++, g++) {
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int flags = g->flags;
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if (flags & GPIO_DEFAULT)
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continue;
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/*
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* If this is a warm reboot, don't set the output levels or
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* we'll shut off the AP.
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*/
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if (is_warm)
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flags &= ~(GPIO_LOW | GPIO_HIGH);
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/* Set up GPIO based on flags */
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gpio_set_flags_by_mask(g->port, g->mask, flags);
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}
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}
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test_mockable int gpio_get_level(enum gpio_signal signal)
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{
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return !!(STM32_GPIO_IDR(gpio_list[signal].port) &
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gpio_list[signal].mask);
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}
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void gpio_set_level(enum gpio_signal signal, int value)
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{
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STM32_GPIO_BSRR(gpio_list[signal].port) =
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gpio_list[signal].mask << (value ? 0 : 16);
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}
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int gpio_enable_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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const struct gpio_info *g_old = gpio_list;
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uint32_t bit, group, shift, bank;
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/* Fail if not implemented or no interrupt handler */
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if (!g->mask || signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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bit = GPIO_MASK_TO_NUM(g->mask);
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g_old += exti_events[bit];
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if ((exti_events[bit]) && (exti_events[bit] != signal)) {
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CPRINTS("Overriding %s with %s on EXTI%d",
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g_old->name, g->name, bit);
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}
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exti_events[bit] = signal;
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group = bit / 4;
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shift = (bit % 4) * 4;
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bank = (g->port - STM32_GPIOA_BASE) / 0x400;
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STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
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~(0xF << shift)) | (bank << shift);
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STM32_EXTI_IMR |= g->mask;
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return EC_SUCCESS;
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}
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int gpio_disable_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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uint32_t bit;
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/* Fail if not implemented or no interrupt handler */
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if (!g->mask || signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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STM32_EXTI_IMR &= ~g->mask;
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bit = GPIO_MASK_TO_NUM(g->mask);
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exti_events[bit] = 0;
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return EC_SUCCESS;
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}
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int gpio_clear_pending_interrupt(enum gpio_signal signal)
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{
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const struct gpio_info *g = gpio_list + signal;
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if (!g->mask || signal >= GPIO_IH_COUNT)
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return EC_ERROR_INVAL;
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STM32_EXTI_PR |= g->mask;
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return EC_SUCCESS;
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}
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/*****************************************************************************/
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/* Interrupt handler */
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void __keep gpio_interrupt(void)
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{
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int bit;
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/* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */
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uint32_t pending = STM32_EXTI_PR & 0xFFFF;
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uint8_t signal;
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STM32_EXTI_PR = pending;
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while (pending) {
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bit = get_next_bit(&pending);
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signal = exti_events[bit];
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if (signal < GPIO_IH_COUNT)
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gpio_irq_handlers[signal](signal);
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}
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}
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#ifdef CHIP_FAMILY_STM32F0
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DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY);
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DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY);
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DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY);
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#endif
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