184 lines
7.3 KiB
C
184 lines
7.3 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI Serial NOR Flash driver module for Chrome EC */
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#ifndef __CROS_EC_SPI_NOR_H
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#define __CROS_EC_SPI_NOR_H
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#include "common.h"
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#include "console.h"
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#include "shared_mem.h"
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#include "task.h"
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#include "util.h"
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/* Driver compatibility requirements based on JEDEC SFDP support:
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*
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* Parameter | SFDP v1.(5+) | SFDP v1.0 | All others
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* ============================================================================
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* Capacity | N/A | N/A | Uses instantiated default
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* --------------------------------------------------------------
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* | The capacity must be less than 4GiB for compatibility.
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* ----------------------------------------------------------------------------
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* Page Size | N/A | 1B or 64B | Uses instantiated default
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* ----------------------------------------------------------------------------
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* Erase Opcodes | 4KiB Erase with an opcode of 0x20 is always required.
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* ----------------------------------------------------------------------------
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* 4B Addressing | 4B addressing mode must be supported if the part is larger
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* | than 16MiB. 4B mode entry will be attempted through opcode
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* | 0xB7 and exit through 0xE9 where writes are enabled for both
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* | in case it is required
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* ----------------------------------------------------------------------------
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*/
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/* Boards which use SPI NOR devices must provide enum spi_device indexing all
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* spi_device_t's in the board.h file. */
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enum spi_device;
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struct spi_nor_device_t {
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/* Name of the Serial NOR Flash device. */
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const char *name;
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/* Index of the SPI master which this device is connected through. */
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const enum spi_device spi_master;
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/* Maximum timeout per command in microseconds. */
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const uint32_t timeout_usec;
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/* when instantiating this device, the initialization values for the
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* following fields will be the default values. Note that the values
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* below may change on the fly based on device state and SFDP
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* discovery. */
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uint32_t capacity;
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size_t page_size;
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int in_4b_addressing_mode;
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};
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extern struct spi_nor_device_t spi_nor_devices[];
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extern const unsigned int spi_nor_devices_used;
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/* Industry standard Serial NOR Flash opcodes. All other opcodes are part
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* specific and require SFDP discovery. */
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#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */
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#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */
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#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */
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#define SPI_NOR_OPCODE_WRITE_DISABLE 0x04
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#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */
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#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06
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#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */
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#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */
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#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */
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#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */
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#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */
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/* Flags for SPI_NOR_OPCODE_READ_STATUS */
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#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */
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#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */
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/* If needed in the future this driver can be extended to discover SFDP
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* advertised erase sizes and opcodes for SFDP v1.0+. */
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#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20
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#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8
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/* If needed in the future this driver can be extended to discover 4B entry and
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* exit methods for SFDP v1.5+. */
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#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7
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#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9
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/* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */
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#define SPI_NOR_JEDEC_ID_BANKS 12
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/**
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* Initialize the module, assumes the Serial NOR Flash devices are currently
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* all available for initialization. As part of the initialization the driver
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* will check if the part has a compatible SFDP Basic Flash Parameter table
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* and update the part's page_size, capacity, and forces the addressing mode.
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* Parts with more than 16MiB of capacity are initialized into 4B addressing
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* and parts with less are initialized into 3B addressing mode.
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*
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* WARNING: This must successfully return before invoking any other Serial NOR
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* Flash APIs.
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*/
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int spi_nor_init(void);
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/**
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* Forces the Serial NOR Flash device to enter (or exit) 4 Byte addressing mode.
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*
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* WARNING:
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* 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
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* 2) If there's a second SPI master communicating with this Serial NOR Flash
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* part on the board, the user is responsible for ensuring addressing mode
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* compatibility and cooperation.
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* 3) The user must ensure that multiple users do not trample on each other
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* by having multiple parties changing the device's addressing mode.
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*
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param enter_4b_addressing_mode Whether to enter (1) or exit (0) 4B mode.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
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int enter_4b_addressing_mode);
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/**
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* Read JEDEC Identifier.
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*
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param size Number of Bytes to read.
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* @param data Destination buffer for data.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
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size_t size, uint8_t *data);
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/**
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* Read from the Serial NOR Flash device.
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*
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param offset Flash offset to read.
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* @param size Number of Bytes to read.
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* @param data Destination buffer for data.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
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uint32_t offset, size_t size, uint8_t *data);
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/**
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* Erase flash on the Serial Flash Device.
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*
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param offset Flash offset to erase, must be aligned to the minimum physical
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* erase size.
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* @param size Number of Bytes to erase, must be a multiple of the the minimum
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* physical erase size.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
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uint32_t offset, size_t size);
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/**
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* Write to the Serial NOR Flash device. Assumes already erased.
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*
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param offset Flash offset to write.
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* @param size Number of Bytes to write.
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* @param data Data to write to flash.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
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uint32_t offset, size_t size, const uint8_t *data);
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/**
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* Write to the extended address register.
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* @param spi_nor_device The Serial NOR Flash device to use.
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* @param value The value to write.
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* @return ec_error_list (non-zero on error and timeout).
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*/
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int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
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const uint8_t value);
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#endif /* __CROS_EC_SPI_NOR_H */
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