185 lines
5.1 KiB
Tcl
185 lines
5.1 KiB
Tcl
# Copyright 2014 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Command automation for NPCX5M5G chip
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# Program spi flash
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source [find mem_helper.tcl]
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proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} {
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set UPLOAD_FLAG 0x200C4000;
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set UUT_TAG 0x200C3000;
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echo "*** NPCX Reset and halt CPU first ***"
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reset halt
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# Clear whole Code RAM
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mwb $cram_addr 0xFF $image_size
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# Upload binary image to Code RAM
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load_image $image_path $cram_addr
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# Upload program spi image FW to lower 16KB Data RAM
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load_image $spifw_image 0x200C3020
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# Set sp to upper 16KB Data RAM
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reg sp 0x200C8000
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# Set spi offset address of uploaded image
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reg r0 $image_offset
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# Set spi program size of uploaded image
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reg r1 $image_size
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# Set pc to start of spi program function
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reg pc 0x200C3021
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# Clear upload flag
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mww $UPLOAD_FLAG 0x0
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# Clear UUT Tag
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mww $UUT_TAG 0x0
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echo "*** Program ... ***"
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# Start to program spi flash
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resume
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# Wait for any pending flash operations to complete
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while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1000 }
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if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} {
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echo "*** Program Fail ***"
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} else {
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echo "*** Program Done ***"
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}
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# Halt CPU
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halt
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}
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proc flash_npcx5m5g {image_path image_offset spifw_image} {
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# 96 KB for RO & RW regions
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set fw_size 0x18000
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# Code RAM start address
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set cram_addr 0x100A8000
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echo "*** Start to program npcx5m5g with $image_path ***"
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flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
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echo "*** Finish program npcx5m5g ***\r\n"
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}
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proc flash_npcx5m6g {image_path image_offset spifw_image} {
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# 224 KB for RO & RW regions
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set fw_size 0x38000
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# Code RAM start address
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set cram_addr 0x10088000
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echo "*** Start to program npcx5m6g with $image_path ***"
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flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
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echo "*** Finish program npcx5m6g ***\r\n"
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}
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proc flash_npcx7m6x {image_path image_offset spifw_image} {
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# 192 KB for RO & RW regions
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set fw_size 0x30000
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# Code RAM start address
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set cram_addr 0x10090000
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echo "*** Start to program npcx7m6f/g/w with $image_path ***"
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flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
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echo "*** Finish program npcx7m6f/g/w ***\r\n"
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}
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proc flash_npcx7m7x {image_path image_offset spifw_image} {
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# 320 KB for RO & RW regions
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set fw_size 0x50000
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# Code RAM start address
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set cram_addr 0x10070000
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echo "*** Start to program npcx7m7f/g/w with $image_path ***"
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flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
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echo "*** Finish program npcx7m7f/g/w ***\r\n"
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}
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proc flash_npcx_ro {chip_name image_dir image_offset} {
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set MPU_RNR 0xE000ED98;
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set MPU_RASR 0xE000EDA0;
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# images path
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set ro_image_path $image_dir/RO/ec.RO.flat
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set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
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# Halt CPU first
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halt
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# disable MPU for Data RAM
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mww $MPU_RNR 0x1
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mww $MPU_RASR 0x0
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if {$chip_name == "npcx_5m5g_jtag"} {
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# program RO region
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flash_npcx5m5g $ro_image_path $image_offset $spifw_image
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} elseif {$chip_name == "npcx_5m6g_jtag"} {
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# program RO region
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flash_npcx5m6g $ro_image_path $image_offset $spifw_image
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} elseif {$chip_name == "npcx_7m6x_jtag"} {
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# program RO region
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flash_npcx7m6x $ro_image_path $image_offset $spifw_image
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} elseif {$chip_name == "npcx_7m7x_jtag"} {
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# program RO region
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flash_npcx7m7x $ro_image_path $image_offset $spifw_image
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} else {
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echo $chip_name "no supported."
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}
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}
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proc flash_npcx_all {chip_name image_dir image_offset} {
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set MPU_RNR 0xE000ED98;
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set MPU_RASR 0xE000EDA0;
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# images path
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set ro_image_path $image_dir/RO/ec.RO.flat
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set rw_image_path $image_dir/RW/ec.RW.bin
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set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
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# Halt CPU first
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halt
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# disable MPU for Data RAM
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mww $MPU_RNR 0x1
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mww $MPU_RASR 0x0
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if {$chip_name == "npcx_5m5g_jtag"} {
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# RW images offset - 128 KB
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set rw_image_offset [expr ($image_offset + 0x20000)]
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# program RO region
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flash_npcx5m5g $ro_image_path $image_offset $spifw_image
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# program RW region
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flash_npcx5m5g $rw_image_path $rw_image_offset $spifw_image
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} elseif {$chip_name == "npcx_5m6g_jtag"} {
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# RW images offset - 256 KB
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set rw_image_offset [expr ($image_offset + 0x40000)]
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# program RO region
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flash_npcx5m6g $ro_image_path $image_offset $spifw_image
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# program RW region
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flash_npcx5m6g $rw_image_path $rw_image_offset $spifw_image
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} elseif {$chip_name == "npcx_7m6x_jtag"} {
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# RW images offset - 256 KB
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set rw_image_offset [expr ($image_offset + 0x40000)]
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# program RO region
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flash_npcx7m6x $ro_image_path $image_offset $spifw_image
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# program RW region
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flash_npcx7m6x $rw_image_path $rw_image_offset $spifw_image
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} elseif {$chip_name == "npcx_7m7x_jtag"} {
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# RW images offset - 512 KB
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set rw_image_offset [expr ($image_offset + 0x80000)]
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# program RO region
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flash_npcx7m7x $ro_image_path $image_offset $spifw_image
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# program RW region
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flash_npcx7m7x $rw_image_path $rw_image_offset $spifw_image
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} else {
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echo $chip_name "no supported."
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}
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}
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proc reset_halt_cpu { } {
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echo "*** NPCX Reset and halt CPU first ***"
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reset halt
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}
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