446 lines
14 KiB
Ada
446 lines
14 KiB
Ada
--
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-- Copyright (C) 2015-2017 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with Ada.Unchecked_Conversion;
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with HW.Debug;
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with GNAT.Source_Info;
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with HW.GFX.DP_Defs;
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use type HW.Word8;
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use type HW.Word16;
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package body HW.GFX.DP_Info is
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procedure Read_Caps
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(Link : in out DP_Link;
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Port : in T;
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Success : out Boolean)
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is
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Data : DP_Defs.Aux_Payload;
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Length : DP_Defs.Aux_Payload_Length;
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Caps_Size : constant := 15;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Length := Caps_Size;
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Aux_Ch.Aux_Read
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(Port => Port,
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Address => 16#00000#,
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Length => Length,
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Data => Data,
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Success => Success);
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Success := Success and Length = Caps_Size;
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if Length = Caps_Size then
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Link.Receiver_Caps.Rev := Data (0);
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case Data (1) is
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when 16#06# =>
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_1_62;
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when 16#0a# =>
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_2_7;
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when 16#14# =>
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_5_4;
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when others =>
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if Data (1) > 16#14# then
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_5_4;
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else
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_1_62;
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end if;
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end case;
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case Data (2) and 16#1f# is
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when 0 | 1 =>
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Link.Receiver_Caps.Max_Lane_Count := DP_Lane_Count_1;
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when 2 | 3 =>
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Link.Receiver_Caps.Max_Lane_Count := DP_Lane_Count_2;
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when others =>
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Link.Receiver_Caps.Max_Lane_Count := DP_Lane_Count_4;
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end case;
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Link.Receiver_Caps.TPS3_Supported := (Data (2) and 16#40#) /= 0;
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Link.Receiver_Caps.Enhanced_Framing := (Data (2) and 16#80#) /= 0;
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Link.Receiver_Caps.No_Aux_Handshake := (Data (3) and 16#40#) /= 0;
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Link.Receiver_Caps.Aux_RD_Interval := Data (14);
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pragma Debug (Debug.New_Line);
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pragma Debug (Debug.Put_Line ("DPCD:"));
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pragma Debug (Debug.Put_Reg8 (" Rev ", Data (0)));
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pragma Debug (Debug.Put_Reg8 (" Max_Link_Rate ", Data (1)));
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pragma Debug (Debug.Put_Reg8 (" Max_Lane_Count ", Data (2) and 16#1f#));
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pragma Debug (Debug.Put_Reg8 (" TPS3_Supported ", Data (2) and 16#40#));
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pragma Debug (Debug.Put_Reg8 (" Enhanced_Framing", Data (2) and 16#80#));
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pragma Debug (Debug.Put_Reg8 (" No_Aux_Handshake", Data (3) and 16#40#));
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pragma Debug (Debug.Put_Reg8 (" Aux_RD_Interval ", Data (14)));
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pragma Debug (Debug.New_Line);
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end if;
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end Read_Caps;
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function Read_LE16
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(Raw_Payload : DP_Defs.Aux_Payload;
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Offset : DP_Defs.Aux_Payload_Index)
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return Word16
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with
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Pre => Offset < DP_Defs.Aux_Payload_Index'Last
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is
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begin
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return Shift_Left (Word16 (Raw_Payload (Offset + 1)), 8) or
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Word16 (Raw_Payload (Offset));
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end Read_LE16;
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procedure Read_eDP_Rates
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(Link : in out DP_Link;
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Port : in T)
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is
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Data : DP_Defs.Aux_Payload;
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Length : DP_Defs.Aux_Payload_Length;
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Max_Rate : Natural;
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Success : Boolean;
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Caps_Size : constant := 3;
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Rates_Size : constant := 16;
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eDP_Rev_1_4 : constant := 3;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Length := Caps_Size;
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Aux_Ch.Aux_Read
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(Port => Port,
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Address => 16#00700#,
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Length => Length,
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Data => Data,
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Success => Success);
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Success := Success and Length = Caps_Size;
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if not Success or Data (0) < eDP_Rev_1_4 then
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return;
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end if;
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Length := Rates_Size;
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Aux_Ch.Aux_Read
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(Port => Port,
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Address => 16#00010#,
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Length => Length,
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Data => Data,
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Success => Success);
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Success := Success and Length = Rates_Size;
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if not Success then
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return;
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end if;
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pragma Debug (Debug.New_Line);
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pragma Debug (Debug.Put_Line ("DPCD eDP 1.4+ link rates:"));
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-- TODO: support individual link rates (storing them all)
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Max_Rate := Natural'First;
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for I in 0 .. Length / 2 - 1 loop
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pragma Loop_Invariant (Max_Rate <= Natural (Word16'Last));
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declare
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Rate : constant Word16 := Read_LE16 (Data, I * 2);
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begin
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exit when Rate = 0; -- prematurely exit the loop
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pragma Debug (Debug.Put (" - "));
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pragma Debug (Debug.Put_Int8 (Int8 (I)));
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pragma Debug (Debug.Put (": "));
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pragma Debug (Debug.Put_Word16 (Rate));
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pragma Debug (Debug.New_Line);
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if Natural (Rate) > Max_Rate then
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Max_Rate := Natural (Rate);
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end if;
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end;
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end loop;
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pragma Debug (Debug.New_Line);
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-- convert to KHz
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Max_Rate := Max_Rate * 20;
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if Max_Rate >= 540_000 then
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_5_4;
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elsif Max_Rate >= 270_000 then
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_2_7;
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elsif Max_Rate >= 162_000 then
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Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_1_62;
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end if;
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end Read_eDP_Rates;
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procedure Minimum_Lane_Count
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(Link : in out DP_Link;
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Mode : in Mode_Type;
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Success : out Boolean)
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with
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Depends => ((Link, Success) => (Link, Mode))
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is
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Lane_Pixel_Per_Second : constant Pos64 :=
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(((DP_Symbol_Rate (Link.Bandwidth) * 8) / 3) / Mode.BPC);
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Count : constant Pos64 :=
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Div_Round_Up (Mode.Dotclock, Lane_Pixel_Per_Second);
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begin
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Success := True;
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case Count is
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when 1 => Link.Lane_Count := DP_Lane_Count_1;
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when 2 => Link.Lane_Count := DP_Lane_Count_2;
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when 3 | 4 => Link.Lane_Count := DP_Lane_Count_4;
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when others => Success := False;
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end case;
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end Minimum_Lane_Count;
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procedure Preferred_Link_Setting
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(Link : in out DP_Link;
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Mode : in Mode_Type;
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Success : out Boolean)
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is
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begin
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Link.Bandwidth := Link.Receiver_Caps.Max_Link_Rate;
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Link.Enhanced_Framing := Link.Receiver_Caps.Enhanced_Framing;
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Minimum_Lane_Count (Link, Mode, Success);
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Success := Success and
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Link.Lane_Count <= Link.Receiver_Caps.Max_Lane_Count;
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pragma Debug (not Success, Debug.Put_Line
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("Mode requirements exceed available bandwidth!"));
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end Preferred_Link_Setting;
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procedure Next_Link_Setting
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(Link : in out DP_Link;
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Mode : in Mode_Type;
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Success : out Boolean)
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is
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begin
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if Link.Bandwidth > DP_Bandwidth'First then
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Link.Bandwidth := DP_Bandwidth'Pred (Link.Bandwidth);
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Minimum_Lane_Count (Link, Mode, Success);
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Success := Success and
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Link.Lane_Count <= Link.Receiver_Caps.Max_Lane_Count;
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else
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Success := False;
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end if;
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end Next_Link_Setting;
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procedure Dump_Link_Setting (Link : DP_Link)
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is
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begin
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Debug.Put ("Trying DP settings: Symbol Rate = ");
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Debug.Put_Int32 (Int32 (DP_Symbol_Rate (Link.Bandwidth)));
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Debug.Put ("; Lane Count = ");
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Debug.Put_Int32 (Int32 (Lane_Count_As_Integer (Link.Lane_Count)));
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Debug.New_Line;
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Debug.New_Line;
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end Dump_Link_Setting;
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----------------------------------------------------------------------------
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procedure Calculate_M_N
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(Link : in DP_Link;
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Mode : in Mode_Type;
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Data_M : out M_Type;
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Data_N : out N_Type;
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Link_M : out M_Type;
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Link_N : out N_Type)
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is
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DATA_N_MAX : constant := 16#800000#;
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LINK_N_MAX : constant := 16#100000#;
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subtype Calc_M_Type is Int64 range 0 .. 2 ** 38;
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subtype Calc_N_Type is Int64 range 0 .. 2 ** 38;
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subtype N_Rounded_Type is Int64 range
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0 .. Int64'Max (DATA_N_MAX, LINK_N_MAX);
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M : Calc_M_Type;
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N : Calc_N_Type;
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procedure Cancel_M_N
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(M : in out Calc_M_Type;
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N : in out Calc_N_Type;
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N_Max : in N_Rounded_Type)
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with
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Depends => ((M, N) => (M, N, N_max)),
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Pre => (N > 0 and M in 0 .. Calc_M_Type'Last / 2),
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Post => (M <= M_N_Max and N <= M_N_Max)
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is
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Orig_N : constant Calc_N_Type := N;
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function Round_N (N : Calc_N_Type) return N_Rounded_Type
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with
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Post => (Round_N'Result <= N * 2)
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is
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RN : Calc_N_Type;
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RN2 : Calc_N_Type := N_Max;
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begin
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loop
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RN := RN2;
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RN2 := RN2 / 2;
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exit when RN2 < N;
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pragma Loop_Invariant (RN2 = RN / 2 and RN2 in N .. N_Max);
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end loop;
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return RN;
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end Round_N;
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begin
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N := Round_N (N);
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-- The automatic provers need a little nudge here.
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pragma Assert
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(if M <= Calc_M_Type'Last/2 and
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N <= Orig_N * 2 and
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Orig_N > 0 and
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M > 0
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then
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M * N / Orig_N <= Calc_M_Type'Last);
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pragma Annotate (GNATprove, False_Positive,
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"assertion might fail",
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"The property cannot be proven automatically. An Isabelle proof is included as an axiom");
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M := M * N / Orig_N;
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-- This loop is never hit for sane values (i.e. M <= N) but
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-- we have to make sure returned values are always in range.
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while M > M_N_Max loop
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pragma Loop_Invariant (N <= M_N_Max);
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M := M / 2;
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N := N / 2;
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end loop;
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end Cancel_M_N;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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pragma Assert (3
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* Mode.BPC
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* Mode.Dotclock
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in Pos64);
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M := 3
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* Mode.BPC
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* Mode.Dotclock;
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pragma Assert (8
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* DP_Symbol_Rate (Link.Bandwidth)
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* Lane_Count_As_Integer (Link.Lane_Count)
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in Pos64);
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N := 8
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* DP_Symbol_Rate (Link.Bandwidth)
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* Lane_Count_As_Integer (Link.Lane_Count);
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Cancel_M_N (M, N, DATA_N_MAX);
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Data_M := M;
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Data_N := N;
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-------------------------------------------------------------------
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M := Pos64 (Mode.Dotclock);
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N := Pos64 (DP_Symbol_Rate (Link.Bandwidth));
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Cancel_M_N (M, N, LINK_N_MAX);
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Link_M := M;
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Link_N := N;
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end Calculate_M_N;
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----------------------------------------------------------------------------
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procedure Read_Link_Status
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(Port : in T;
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Status : out Link_Status;
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Success : out Boolean)
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is
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subtype Status_Index is DP_Defs.Aux_Payload_Index range 0 .. 5;
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subtype Status_Buffer is Buffer (Status_Index);
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function Buffer_As_Status is new Ada.Unchecked_Conversion
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(Source => Status_Buffer, Target => Link_Status);
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Data : DP_Defs.Aux_Payload;
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Length : DP_Defs.Aux_Payload_Length;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Length := Status_Index'Last + 1;
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Aux_Ch.Aux_Read
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(Port => Port,
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Address => 16#00202#,
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Length => Length,
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Data => Data,
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Success => Success);
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Success := Success and Length = Status_Index'Last + 1;
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Status := Buffer_As_Status (Data (Status_Index));
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end Read_Link_Status;
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function All_CR_Done
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(Status : Link_Status;
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Link : DP_Link)
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return Boolean
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is
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CR_Done : Boolean := True;
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begin
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for Lane in Lane_Index
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range 0 .. Lane_Index (Lane_Count_As_Integer (Link.Lane_Count) - 1)
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loop
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CR_Done := CR_Done and Status.Lanes (Lane).CR_Done;
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end loop;
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return CR_Done;
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end All_CR_Done;
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function All_EQ_Done
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(Status : Link_Status;
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Link : DP_Link)
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return Boolean
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is
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EQ_Done : Boolean := True;
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begin
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for Lane in Lane_Index
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range 0 .. Lane_Index (Lane_Count_As_Integer (Link.Lane_Count) - 1)
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loop
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EQ_Done := EQ_Done and Status.Lanes (Lane).CR_Done
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and Status.Lanes (Lane).Channel_EQ_Done
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and Status.Lanes (Lane).Symbol_Locked;
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end loop;
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return EQ_Done and Status.Interlane_Align_Done;
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end All_EQ_Done;
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function Max_Requested_VS
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(Status : Link_Status;
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Link : DP_Link)
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return DP_Voltage_Swing
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is
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VS : DP_Voltage_Swing := DP_Voltage_Swing'First;
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begin
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for Lane in Lane_Index
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range 0 .. Lane_Index (Lane_Count_As_Integer (Link.Lane_Count) - 1)
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loop
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if Status.Adjust_Requests (Lane).Voltage_Swing > VS then
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VS := Status.Adjust_Requests (Lane).Voltage_Swing;
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end if;
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end loop;
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return VS;
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end Max_Requested_VS;
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function Max_Requested_Emph
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(Status : Link_Status;
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Link : DP_Link)
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return DP_Pre_Emph
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is
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Emph : DP_Pre_Emph := DP_Pre_Emph'First;
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begin
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for Lane in Lane_Index
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range 0 .. Lane_Index (Lane_Count_As_Integer (Link.Lane_Count) - 1)
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loop
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if Status.Adjust_Requests (Lane).Pre_Emph > Emph then
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Emph := Status.Adjust_Requests (Lane).Pre_Emph;
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end if;
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end loop;
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return Emph;
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end Max_Requested_Emph;
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end HW.GFX.DP_Info;
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