95 lines
5.1 KiB
C
95 lines
5.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_FP_H__
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#define __RISCV_FP_H__
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_types.h>
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#define GET_PRECISION(insn) (((insn) >> 25) & 3)
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define PRECISION_S 0
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#define PRECISION_D 1
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#ifdef __riscv_flen
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#define GET_F32_REG(insn, pos, regs) \
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({ \
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register s32 value asm("a0") = \
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SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp), "+&r"(value)::"t0"); \
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value; \
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})
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#define SET_F32_REG(insn, pos, regs, val) \
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({ \
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register u32 value asm("a0") = (val); \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile( \
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"1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp) \
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: "r"(value), "r"(offset) \
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: "t0"); \
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})
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#define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0)
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#define GET_F64_REG(insn, pos, regs) \
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({ \
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register ulong value asm("a0") = \
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SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp), "+&r"(value)::"t0"); \
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sizeof(ulong) == 4 ? *(int64_t *)value : (int64_t)value; \
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})
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#define SET_F64_REG(insn, pos, regs, val) \
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({ \
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uint64_t __val = (val); \
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register ulong value asm("a0") = \
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sizeof(ulong) == 4 ? (ulong)&__val : (ulong)__val; \
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ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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ulong tmp; \
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asm volatile( \
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"1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
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: "=&r"(tmp) \
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: "r"(value), "r"(offset) \
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: "t0"); \
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})
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#define GET_FCSR() csr_read(CSR_FCSR)
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#define SET_FCSR(value) csr_write(CSR_FCSR, (value))
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#define GET_FRM() csr_read(CSR_FRM)
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#define SET_FRM(value) csr_write(CSR_FRM, (value))
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#define GET_FFLAGS() csr_read(CSR_FFLAGS)
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#define SET_FFLAGS(value) csr_write(CSR_FFLAGS, (value))
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#define SET_FS_DIRTY() ((void)0)
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#define GET_F32_RS1(insn, regs) (GET_F32_REG(insn, 15, regs))
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#define GET_F32_RS2(insn, regs) (GET_F32_REG(insn, 20, regs))
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#define GET_F32_RS3(insn, regs) (GET_F32_REG(insn, 27, regs))
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#define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs))
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#define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs))
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#define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs))
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#define SET_F32_RD(insn, regs, val) \
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(SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define SET_F64_RD(insn, regs, val) \
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(SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs))
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#define GET_F32_RS2S(insn, regs) (GET_F32_REG(RVC_RS2S(insn), 0, regs))
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#define GET_F64_RS2C(insn, regs) (GET_F64_REG(insn, 2, regs))
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#define GET_F64_RS2S(insn, regs) (GET_F64_REG(RVC_RS2S(insn), 0, regs))
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#endif
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#endif
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