112 lines
2.2 KiB
C
112 lines
2.2 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* LLC driver is the Last Level Cache (L3C) driver
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* for Marvell SoCs in AP806, AP807, and AP810
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <drivers/marvell/cache_llc.h>
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#include <drivers/marvell/ccu.h>
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#include <lib/mmio.h>
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#include <mvebu_def.h>
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#define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200)
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#define CCU_SET_POC_OFFSET 5
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extern void ca72_l2_enable_unique_clean(void);
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void llc_cache_sync(int ap_index)
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{
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mmio_write_32(LLC_SYNC(ap_index), 0);
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/* Atomic write, no need to wait */
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}
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void llc_flush_all(int ap_index)
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{
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mmio_write_32(L2X0_CLEAN_INV_WAY(ap_index), LLC_WAY_MASK);
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llc_cache_sync(ap_index);
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}
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void llc_clean_all(int ap_index)
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{
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mmio_write_32(L2X0_CLEAN_WAY(ap_index), LLC_WAY_MASK);
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llc_cache_sync(ap_index);
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}
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void llc_inv_all(int ap_index)
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{
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mmio_write_32(L2X0_INV_WAY(ap_index), LLC_WAY_MASK);
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llc_cache_sync(ap_index);
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}
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void llc_disable(int ap_index)
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{
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llc_flush_all(ap_index);
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mmio_write_32(LLC_CTRL(ap_index), 0);
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dsbishst();
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}
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void llc_enable(int ap_index, int excl_mode)
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{
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uint32_t val;
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dsbsy();
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llc_inv_all(ap_index);
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dsbsy();
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val = LLC_CTRL_EN;
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if (excl_mode)
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val |= LLC_EXCLUSIVE_EN;
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mmio_write_32(LLC_CTRL(ap_index), val);
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dsbsy();
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}
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int llc_is_exclusive(int ap_index)
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{
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uint32_t reg;
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reg = mmio_read_32(LLC_CTRL(ap_index));
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if ((reg & (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) ==
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(LLC_CTRL_EN | LLC_EXCLUSIVE_EN))
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return 1;
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return 0;
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}
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void llc_runtime_enable(int ap_index)
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{
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uint32_t reg;
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reg = mmio_read_32(LLC_CTRL(ap_index));
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if (reg & LLC_CTRL_EN)
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return;
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INFO("Enabling LLC\n");
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/*
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* Enable L2 UniqueClean evictions with data
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* Note: this configuration assumes that LLC is configured
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* in exclusive mode.
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* Later on in the code this assumption will be validated
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*/
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ca72_l2_enable_unique_clean();
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llc_enable(ap_index, 1);
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/* Set point of coherency to DDR.
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* This is required by units which have SW cache coherency
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*/
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reg = mmio_read_32(CCU_HTC_CR(ap_index));
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reg |= (0x1 << CCU_SET_POC_OFFSET);
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mmio_write_32(CCU_HTC_CR(ap_index), reg);
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}
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